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Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)最新文献

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Design methodology of a 200 MHz superscalar macroprocessor: SH-4 SH-4型200mhz超标量宏处理器的设计方法
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-06-15 DOI: 10.1109/DAC.1998.724475
T. Hattori, Y. Nitta, M. Seki, S. Narita, K. Uchiyama, T. Takahashi, R. Satomura
{"title":"Design methodology of a 200 MHz superscalar macroprocessor: SH-4","authors":"T. Hattori, Y. Nitta, M. Seki, S. Narita, K. Uchiyama, T. Takahashi, R. Satomura","doi":"10.1109/DAC.1998.724475","DOIUrl":"https://doi.org/10.1109/DAC.1998.724475","url":null,"abstract":"A new design methodology focusing on high speed operation and short design time is described for the SH-4 200 MHz superscalar microprocessor. Random test generation, logic emulation, and formal verification are applied to logic verification for shortening design time. Delay budgeting, forward/back annotation, and clock design are key features for timing driven design.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122229848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Rate optimal VLSI design from data flow graph 从数据流图中评估最佳VLSI设计
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-06-15 DOI: 10.1109/DAC.1998.724451
Moonwook Oh, S. Ha
{"title":"Rate optimal VLSI design from data flow graph","authors":"Moonwook Oh, S. Ha","doi":"10.1109/DAC.1998.724451","DOIUrl":"https://doi.org/10.1109/DAC.1998.724451","url":null,"abstract":"This paper considers the rate optimal VLSI design of a recursive data flow graph (DFG). Previous research on rate optimal scheduling is not directly applicable to VLSI design. We propose a technique that inserts buffer registers to allow overlapped rate optimal implementation of VLSI. We illustrate that nonoverlapped schedules can be implemented by a simpler control path but with a larger unfolding factor, if it exists, than overlapped schedules.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127803878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
What's between simulation and formal verification? 模拟和正式验证之间有什么区别?
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-06-15 DOI: 10.1109/DAC.1998.724491
D. L. Dill
{"title":"What's between simulation and formal verification?","authors":"D. L. Dill","doi":"10.1109/DAC.1998.724491","DOIUrl":"https://doi.org/10.1109/DAC.1998.724491","url":null,"abstract":"This embedded tutorial surveys some possibilities for verification techniques that combine conventional simulation and ideas, techniques, and algorithms from formal verification, to obtain better functional test coverage of large designs.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114675021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions 从分层高层描述合成的控制器分区和优化
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277239
A. Seawright, W. Meyer
{"title":"Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions","authors":"A. Seawright, W. Meyer","doi":"10.1145/277044.277239","DOIUrl":"https://doi.org/10.1145/277044.277239","url":null,"abstract":"This paper describes methods for partitioning and optimizing controllers described by hierarchical high-level descriptions. The methods utilize the structure of the high-level description, provide flexible exploration of the trade-off between combinational logic and registers to reduce implementation cost, and allow the designer to control the synthesis process. Results are presented using industrial examples.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115219535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Reducing power in high-performance microprocessors 降低高性能微处理器的功耗
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277227
V. Tiwari, Deo Singh, S. Rajgopal, G. Mehta, Rakesh J. Patel, F. Baez
{"title":"Reducing power in high-performance microprocessors","authors":"V. Tiwari, Deo Singh, S. Rajgopal, G. Mehta, Rakesh J. Patel, F. Baez","doi":"10.1145/277044.277227","DOIUrl":"https://doi.org/10.1145/277044.277227","url":null,"abstract":"Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. Designers are thus continuously challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design. This paper presents an overview of the issues related to power consumption in the context of Intel CPUs. The main trends that are driving the increased focus on design for low power are described. System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described. The role of CAD tools and their limitations in this domain are also discussed. In addition, areas that need increased research focus in the future are also pointed out.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116018669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 377
Functional verification of large ASICs 大型asic的功能验证
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277210
A. Evans, A. Silburt, G. Vrckovnik, T. Brown, M. Dufresne, G. Hall, Tung Ho, Y. Liu
{"title":"Functional verification of large ASICs","authors":"A. Evans, A. Silburt, G. Vrckovnik, T. Brown, M. Dufresne, G. Hall, Tung Ho, Y. Liu","doi":"10.1145/277044.277210","DOIUrl":"https://doi.org/10.1145/277044.277210","url":null,"abstract":"This paper describes the functional verification effort during a specific hardware development program that included three of the largest ASPCs designed at Nortel. These devices marked a transition point in methodology as verification took front and centre on the critical path of the ASIC schedule. Both the simulation and emulation strategies are presented. The simulation methodology introduced new techniques such as ASIC sub-system level behavioural modeling, large multi-chip simulations, and random pattern simulations. The emulation strategy was based on a plan that consisted of integrating parts of the real software on the emulated system. This paper describes how these technologies were deployed, analyzes the bugs that were found and highlights the bottlenecks in functional verification as systems become more complex.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"372 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129082073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Design and specification of embedded systems in Java using successive, formal refinement 在Java中使用连续的、形式化的细化来设计和规范嵌入式系统
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277058
James Shin Young, Josh MacDonald, Michael Shilman, A. Tabbara, P. Hilfinger, A. R. Newton
{"title":"Design and specification of embedded systems in Java using successive, formal refinement","authors":"James Shin Young, Josh MacDonald, Michael Shilman, A. Tabbara, P. Hilfinger, A. R. Newton","doi":"10.1145/277044.277058","DOIUrl":"https://doi.org/10.1145/277044.277058","url":null,"abstract":"Successive, formal refinement is a new approach for specification of embedded systems using a general-purpose programming language. Systems are formally modeled as abstractable synchronous reactive systems, and Java is used as the design input language. A policy of use is applied to Java, in the form of language usage restrictions and class-library extensions to ensure consistency with the formal model. A process of incremental, user-guided program transformation is used to refine a Java program until it is consistent with the policy of use. The final product is a system specification possessing the properties of the formal model, including deterministic behavior, bounded memory usage and bounded execution time. This approach allows systems design to begin with the flexibility of a general-purpose language, followed by gradual refinement into a more restricted form necessary for specification.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126801631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
A multiprocessor DSP system using PADDI-2 基于padi -2的多处理器DSP系统
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277056
R. A. Sutton, V. P. Srini, J. Rabaey
{"title":"A multiprocessor DSP system using PADDI-2","authors":"R. A. Sutton, V. P. Srini, J. Rabaey","doi":"10.1145/277044.277056","DOIUrl":"https://doi.org/10.1145/277044.277056","url":null,"abstract":"We have integrated an image processing system built around PADDI-2, a custom 48 node MIMD parallel DSP. The system includes image processing algorithms, a graphical SFG tool, a simulator, routing tools, compilers, hardware configuration and debugging tools, application development libraries, and software implementations for hardware verification. The system board, connected to a SPARCstation via a custom Sbus controller, contains 384 processors in 8 VLSI chips. The software environment supports a multiprocessor system under development (VGI-1). The software tools and libraries are modular, with implementation dependencies isolated in layered encapsulations.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121709968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Table-lookup methods for improved performance-driven routing 改进性能驱动路由的表查找方法
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277146
J. Lillis, Premal Buch
{"title":"Table-lookup methods for improved performance-driven routing","authors":"J. Lillis, Premal Buch","doi":"10.1145/277044.277146","DOIUrl":"https://doi.org/10.1145/277044.277146","url":null,"abstract":"The inaccuracy of Elmore delay for interconnect delay estimation is well-documented. However it remains a popular delay measure to drive performance optimization procedures such as wire-sizing and topology construction. This paper studies the merits of incorporating \"better-than-Elmore\" delay measures into the optimization process. The proposed delay metrics use a table-lookup method to incorporate better load modeling and approximate the effect of signal slew. We demonstrate that the proposed metrics exhibit a much narrower error distribution than Elmore delay, eliminating Elmore's frequent gross delay over-estimation. Finally we show the improvement in solution quality which can be had by incorporating the new metrics into a timing driven topology construction algorithm.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"45 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114022764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Compatible class encoding in hyper-function decomposition for FPGA synthesis FPGA合成超功能分解中的兼容类编码
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277223
J. H. Jiang, Jing-Yang Jou, Juinn-Dar Huang
{"title":"Compatible class encoding in hyper-function decomposition for FPGA synthesis","authors":"J. H. Jiang, Jing-Yang Jou, Juinn-Dar Huang","doi":"10.1145/277044.277223","DOIUrl":"https://doi.org/10.1145/277044.277223","url":null,"abstract":"Recently, functional decomposition has been adopted for LUT based FPGA technology mapping with good results. In this paper, we propose a novel method for functional multiple-output decomposition. We first address a compatible class encoding method to minimize the compatible classes in the image function. After the encoding algorithm is applied, the decomposability will be improved in the subsequent decomposition of the image function. The above encoding algorithm is then extended to encode multiple-output functions through the construction of a hyper-function. Common sub-expressions among these multiple-output functions can be extracted during the decomposition of the hyper-function. Therefore, we can handle the multiple-output decomposition in the same manner as the single-output decomposition. Experimental results show that our algorithms are very promising.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127592232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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