Design methodology of a 200 MHz superscalar macroprocessor: SH-4

Abstract

A new design methodology focusing on high speed operation and short design time is described for the SH-4 200 MHz superscalar microprocessor. Random test generation, logic emulation, and formal verification are applied to logic verification for shortening design time. Delay budgeting, forward/back annotation, and clock design are key features for timing driven design.