从数据流图中评估最佳VLSI设计

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-06-15 DOI:10.1109/DAC.1998.724451

Moonwook Oh, S. Ha

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引用次数: 7

摘要

本文研究递归数据流图(DFG)的速率最优VLSI设计。以往关于速率最优调度的研究并不直接适用于超大规模集成电路设计。我们提出了一种插入缓冲寄存器的技术，以允许超大规模集成电路的重叠率优化实现。我们说明了非重叠调度可以通过一个更简单的控制路径来实现，但如果它存在，则具有比重叠调度更大的展开因子。

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Rate optimal VLSI design from data flow graph

This paper considers the rate optimal VLSI design of a recursive data flow graph (DFG). Previous research on rate optimal scheduling is not directly applicable to VLSI design. We propose a technique that inserts buffer registers to allow overlapped rate optimal implementation of VLSI. We illustrate that nonoverlapped schedules can be implemented by a simpler control path but with a larger unfolding factor, if it exists, than overlapped schedules.

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Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

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