SH-4型200mhz超标量宏处理器的设计方法

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-06-15 DOI:10.1109/DAC.1998.724475

T. Hattori, Y. Nitta, M. Seki, S. Narita, K. Uchiyama, T. Takahashi, R. Satomura

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引用次数: 0

摘要

介绍了SH-4 200mhz超大规模微处理器的高速运行和短设计时间的设计方法。逻辑验证采用随机测试生成、逻辑仿真和形式化验证，缩短了设计时间。延迟预算、向前/向后注释和时钟设计是时间驱动设计的关键特性。

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Design methodology of a 200 MHz superscalar macroprocessor: SH-4

A new design methodology focusing on high speed operation and short design time is described for the SH-4 200 MHz superscalar microprocessor. Random test generation, logic emulation, and formal verification are applied to logic verification for shortening design time. Delay budgeting, forward/back annotation, and clock design are key features for timing driven design.

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Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

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