Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)最新文献_第9页

Hybrid techniques for fast functional simulation 快速功能仿真的混合技术

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724554

Yufeng Luo, T. Wongsonegoro, A. Aziz

引用次数: 17

A programming environment for the design of complex high speed ASICs 一种用于设计复杂高速asic的编程环境

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277135

P. Schaumont, S. Vernalde, L. Rijnders, M. Engels, I. Bolsens

引用次数: 94

Tools and methodology for RF IC design 射频集成电路设计的工具和方法

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277155

A. Dunlop, A. Demir, P. Feldmann, S. Kapur, D. Long, R. Melville, J. Roychowdhury

引用次数: 21

Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions 将推测性执行纳入控制流密集行为描述的调度

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277067

G. Lakshminarayana, A. Raghunathan, N. Jha

{"title":"Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions","authors":"G. Lakshminarayana, A. Raghunathan, N. Jha","doi":"10.1145/277044.277067","DOIUrl":"https://doi.org/10.1145/277044.277067","url":null,"abstract":"Speculative execution refers to the execution of parts of a computation before the execution of the conditional operations that decide whether it needs to be executed. It has been shown to be a promising technique for eliminating performance bottlenecks imposed by control flow in hardware and software implementations alike. In this paper, we present techniques to incorporate speculative execution in a fine-grained manner into scheduling of control-how intensive behavioral descriptions. We demonstrate that failing to take into account information such as resource constraints and branch probabilities can lead to significantly sub-optimal performance. We also demonstrate that it may be necessary to speculate simultaneously along multiple paths, subject to resource constraints, in order to minimize the delay overheads incurred when prediction errors occur. Experimental results on several benchmarks show that our speculative scheduling algorithm can result in significant (up to seven-fold) improvements in performance (measured in terms of the average number of clock cycles) as compared to scheduling without speculative execution. Also, the best and worst case execution times for the speculatively performed schedules are the same as or better than the corresponding values for the schedules obtained without speculative execution.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130166235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

HW/SW CoVerification performance estimation and benchmark for a 24 embedded RISC core design 24嵌入式RISC核心设计的硬件/软件覆盖率性能评估和基准测试

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277250

T. Albrecht, J. Notbauer, S. Rohringer

引用次数: 20

Realization of a programmable parallel DSP for high performance image processing applications 实现了一种可编程并行DSP的高性能图像处理应用

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277055

J. Wittenburg, W. Hinrichs, J. Kneip, M. Ohmacht, Mladen Berekovic, H. Lieske, H. Kloos, P. Pirsch

引用次数: 11

Adjoint transient sensitivity computation in piecewise linear simulation 分段线性模拟中伴随瞬态灵敏度的计算

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277177

Tuyen V. Nguyen, A. Devgan, Ognen J. Nastov

引用次数: 12

Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator 指令选择，资源分配和调度在AVIV可重目标代码生成器

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277184

S. Hanono, S. Devadas

{"title":"Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator","authors":"S. Hanono, S. Devadas","doi":"10.1145/277044.277184","DOIUrl":"https://doi.org/10.1145/277044.277184","url":null,"abstract":"The AVIV retargetable code generator produces optimized machine code for target processors with different instruction set architectures. AVIV optimizes for minimum code size. Retargetable code generation requires the development of heuristic algorithms for instruction selection, resource allocation, and scheduling. AVIV addresses these code generation subproblems concurrently, whereas most current code generation systems address them sequentially. It accomplishes this by converting the input application to a graphical (Split-Node DAG) representation that specifies all possible ways of implementing the application on the target processor. The information embedded in this representation is then used to set up a heuristic branch-and-bound step that performs functional unit assignment, operation grouping, register bank allocation, and scheduling concurrently. While detailed register allocation is carried out as a second step, estimates of register requirements are generated during the first step to ensure high quality of the final assembly code. We show that near-optimal code can be generated for basic blocks for different architectures within reasonable amounts of CPU time. Our framework thus allows us to accurately evaluate the performance of different architectures on application code.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130843249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 124

Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions 基于分层行为描述的功率优化和面积优化电路的综合

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277167

G. Lakshminarayana, N. Jha

{"title":"Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions","authors":"G. Lakshminarayana, N. Jha","doi":"10.1145/277044.277167","DOIUrl":"https://doi.org/10.1145/277044.277167","url":null,"abstract":"We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex RTL modules, such as FFTs and filters, as building blocks for the RTL circuit, in addition to simple RTL modules such as adders and multipliers. Unlike past techniques in the area, we also customize the complex RTL modules to match the environment in which they find themselves. We present a fast and efficient algorithm for mapping multiple behaviors onto the same RTL module during the course of synthesis, thus allowing our synthesis system to explore previously unexplored regions of the design space. These techniques are at the core of an iterative improvement based approach which can accept temporary degradation in solution quality in its quest for a globally optimal solution. The moves in our iterative improvement procedure explore optimizations along different dimensions such as functional unit selection, resource allocation, resource sharing, resource splitting, and selection and resynthesis of complex RTL modules. These inter-related optimizations are dynamically traded off with each other during the course of synthesis, thus exploiting the benefits that arise from their interaction. The synthesis framework also tackles other related high-level synthesis tasks such as scheduling, clock selection, and V/sub dd/ selection. Experimental results demonstrate that our algorithm produces circuits whose area and power consumption are comparable to or better than those produced using flattened synthesis, within much shorter CPU times. The efficacy of our algorithm in the power-optimization mode is illustrated by the fact that it produces circuits that consume up to 6.7 times less power than area-optimized circuits working at 5 Volts at area overheads not exceeding 50%.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131838155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Hierarchical algorithms for assessing probabilistic constraints on system performance 评估系统性能的概率约束的分层算法

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277113

G. Veciana, M. Jacome, Jian-Huei Guo

引用次数: 10