HW/SW CoVerification performance estimation and benchmark for a 24 embedded RISC core design

Abstract

This paper describes the benchmarking of a HW/SW-coverification design strategy. The benchmark results were the base for making a principal verification decision for an already ongoing project at Siemens AG, Public Communication Network Group. The intention for this benchmark was to verify whether commercial available coverification tools can handle the design complexity of an embedded system containing 24 embedded RISC cores and provides the necessary performance in terms of simulation speed and throughput.