Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)最新文献_第4页

Validation with guided search of the state space 使用状态空间的引导搜索进行验证

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277201

H. Yang, D. Dill

引用次数: 179

M32: a constructive multilevel logic synthesis system M32:一个建设性的多层逻辑综合系统

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277140

Victor N. Kravets, K. Sakallah

引用次数: 15

A fast hierarchical algorithm for 3-D capacitance extraction 三维电容提取的快速分层算法

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724469

Weiping Shi, Jianguo Liu, N. Kakani, T. Yu

{"title":"A fast hierarchical algorithm for 3-D capacitance extraction","authors":"Weiping Shi, Jianguo Liu, N. Kakani, T. Yu","doi":"10.1109/DAC.1998.724469","DOIUrl":"https://doi.org/10.1109/DAC.1998.724469","url":null,"abstract":"We present a new algorithm for computing the capacitance of three-dimensional perfect electrical conductors of complex structures. The new algorithm is significantly faster and uses much less memory than previous best algorithms, and is kernel independent. The new algorithm is based on a hierarchical algorithm for the n-body problem, and is an acceleration of the boundary element method for solving the integral equation associated with the capacitance extraction problem. The algorithm first adaptively subdivides the conductor surfaces into panels according to an estimation of the potential coefficients and a user-supplied error bound. The algorithm stores the potential coefficient matrix in a hierarchical data structure of size O(n), although the matrix is size n/sup 2/ if expanded explicitly, where n is the number of panels. The hierarchical data structure allows us to multiply the coefficient matrix with any vector in O(n) time. Finally, we use a generalized minimal residual algorithm to solve m linear systems each of size n/spl times/n in O(mn) time, where m is the number of conductors. The new algorithm is implemented and the performance is compared with previous best algorithms. For the k/spl times/k bus example, our algorithm is 100 to 40 times faster than FastCap, and uses 1/100 to 1/60 of the memory used by FastCap. The results computed by the new algorithm are within 2.7% from that computed by FastCap.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131403887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 106

A BIST scheme for RTL controller-data paths based on symbolic testability analysis 基于符号可测试性分析的RTL控制器数据路径的BIST方案

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277192

Indradeep Ghosh, N. Jha, S. Bhawmik

{"title":"A BIST scheme for RTL controller-data paths based on symbolic testability analysis","authors":"Indradeep Ghosh, N. Jha, S. Bhawmik","doi":"10.1145/277044.277192","DOIUrl":"https://doi.org/10.1145/277044.277192","url":null,"abstract":"This paper introduces a novel scheme for testing register-transfer level controller/data paths using built-in self-test (BIST). The scheme uses the controller netlist and the data path of a circuit to extract a test control/data flow (TCDF) which consists of operations mapped to modules in the circuit and variables mapped to registers. This TCDF is used to derive a set of symbolic justification and propagation paths (known as test environment) to test some of the operations and variables present in it. If it becomes difficult to generate such test environments with the derived TCDFs, a few test multiplexers are added at suitable points in the circuit to increase its controllability and observability. This test environment can then be used to exercise a module or register in the circuit with pseudorandom pattern generators which are placed only at the primary inputs of the circuit. The test responses can be analyzed with signature analyzers which are only placed at the primary outputs of the circuit. Every module in the module library is made random-pattern testable, whenever possible, using gate-level testability insertion techniques. Finally a BIST controller is synthesized to provide the necessary control signals to form the different test environments during testing, and a BIST architecture is superimposed an the circuit. Experimental results on a number of industrial and university benchmarks show that high fault coverage (>99%) can be obtained with our scheme in a small number of test cycles at an average area (delay) overhead of only 6.4% (2.5 %).","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127623947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Arithmetic optimization using carry-save-adders 使用进位节省加法器的算法优化

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724511

Taewhan Kim, W. Jao, S. Tjiang

引用次数: 44

Process multi-circuit optimization 工艺多电路优化

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277149

A. Lokanathan, J. Brockman

引用次数: 0

Timing and crosstalk driven area routing 时序和串扰驱动区域路由

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277148

Hsiao-Ping Tseng, L. Scheffer, C. Sechen

引用次数: 93

A statistical performance simulation methodology for VLSI circuits VLSI电路的统计性能仿真方法

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277153

M. Orshansky, James C. Chen, C. Hu

引用次数: 12

A power macromodeling technique based on power sensitivity 一种基于功率灵敏度的功率宏建模技术

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724557

Zhanping Chen, K. Roy

{"title":"A power macromodeling technique based on power sensitivity","authors":"Zhanping Chen, K. Roy","doi":"10.1109/DAC.1998.724557","DOIUrl":"https://doi.org/10.1109/DAC.1998.724557","url":null,"abstract":"We propose a novel power macromodeling technique for high level power estimation based on power sensitivity. Power sensitivity defines the change in average power due to changes in the input signal specification. The contribution of this work is that we can use only a few points to construct a complicated power surface in the specification-space. With such a power surface, we can easily obtain the power dissipation under any distribution of primary inputs. The advantages of our technique are two-fold. First, the required parameters corresponding to each representative point can be efficiently obtained by only one symbolic power estimation run or by only one Monte Carlo based statistical power estimation process. This stems from the fact that power sensitivity can be obtained as a by-product of probabilistic or statistical power estimation runs. Second, the memory requirements for the macromodel are reduced to O(dn), where n is the number of primary inputs of a circuit and d is the number of representative points (d can be as small as 1 in some cases). Results on a number of benchmark circuits demonstrate the effectiveness of our technique.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121417891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 64

Delay estimation of VLSI circuits from a high-level view VLSI电路的高阶延迟估计

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277199

M. Nemani, F. Najm

引用次数: 14