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Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)最新文献

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An implicit algorithm for finding steady states and its application to FSM verification 一种求稳定状态的隐式算法及其在FSM验证中的应用
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277203
Gagan Hasteer, Anmol Mathur, P. Banerjee
{"title":"An implicit algorithm for finding steady states and its application to FSM verification","authors":"Gagan Hasteer, Anmol Mathur, P. Banerjee","doi":"10.1145/277044.277203","DOIUrl":"https://doi.org/10.1145/277044.277203","url":null,"abstract":"Finding the set of steady states of a machine has applications in formal verification, sequential synthesis and ATPG. Existing techniques assume the presence of a designated set of initial states which is impractical in a real design environment. The set steady states of a design is defined by the terminally strongly connected components (tSCCs) of the underlying state transition graph (STG). We show that multiple tSCCs and non-terminal CCs need to be handled in a real design environment especially for verification. We present a fully implicit algorithm to find the steady states of a machine without any knowledge of initial states. We demonstrate the utility of our algorithm by applying it to FSM equivalence checking.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127513328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Policy optimization for dynamic power management 动态电源管理策略优化
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277094
L. Benini, A. Bogliolo, Giuseppe A. Paleologo, G. Micheli
{"title":"Policy optimization for dynamic power management","authors":"L. Benini, A. Bogliolo, Giuseppe A. Paleologo, G. Micheli","doi":"10.1145/277044.277094","DOIUrl":"https://doi.org/10.1145/277044.277094","url":null,"abstract":"Dynamic power management schemes (also called policies) can be used to control the power consumption levels of electronic systems, by setting their components in different states, each characterized by a performance level and a power consumption. In this paper, we describe power-managed systems using a finite-state, stochastic model. Furthermore, we show that the fundamental problem of finding an optimal policy which maximizes the average performance level of a system, subject to a constraint on the power consumption, can be formulated as a stochastic optimization problem called policy optimization. Policy optimization can be solved exactly in polynomial time (in the number of states of the model). We implemented a policy optimization tool and tested the quality of the optimal policies on a realistic case study.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129916162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 524
Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques 利用电压缩放技术的超低功耗MPEG4编解码器核心设计方法
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277178
K. Usami, M. Igarashi, T. Ishikawa, M. Kanazawa, Masafumi Takahashi, M. Hamada, H. Arakida, T. Terazawa, T. Kuroda
{"title":"Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques","authors":"K. Usami, M. Igarashi, T. Ishikawa, M. Kanazawa, Masafumi Takahashi, M. Hamada, H. Arakida, T. Terazawa, T. Kuroda","doi":"10.1145/277044.277178","DOIUrl":"https://doi.org/10.1145/277044.277178","url":null,"abstract":"This paper describes a fully automated low-power design methodology in which three different voltage-scaling techniques are combined together. Supply voltage is scaled globally, selectively, and adaptively while keeping the performance. This methodology enabled us to design an MPEG4 codec core with 58% less power than the original in three week turn-around-time.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129972140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
Robust IP watermarking methodologies for physical design 物理设计的鲁棒IP水印方法
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277241
A. Kahng, S. Mantik, I. Markov, M. Potkonjak, P. Tucker, Huijuan Wang, Gregory Wolfe
{"title":"Robust IP watermarking methodologies for physical design","authors":"A. Kahng, S. Mantik, I. Markov, M. Potkonjak, P. Tucker, Huijuan Wang, Gregory Wolfe","doi":"10.1145/277044.277241","DOIUrl":"https://doi.org/10.1145/277044.277241","url":null,"abstract":"Increasingly popular reuse-based design paradigms create a pressing need for authorship enforcement techniques that protect the intellectual property rights of designers. We develop the first intellectual property protection protocols for embedding design watermarks at the physical design level. We demonstrate that these protocols are transparent with respect to existing industrial tools and design flows, and that they can embed watermarks into real-world industrial designs with very low implementation overhead (as measured by such standard metrics as wirelength, layout area, number of vias, routing congestion and CPU time). On several industrial test cases, we obtain extremely strong, tamper-resistant proofs of authorship for placement and routing solutions.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"527 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132417196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 127
A methodology for guided behavioral-level optimization 引导行为级优化的方法
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277134
L. Guerra, M. Potkonjak, J. Rabaey
{"title":"A methodology for guided behavioral-level optimization","authors":"L. Guerra, M. Potkonjak, J. Rabaey","doi":"10.1145/277044.277134","DOIUrl":"https://doi.org/10.1145/277044.277134","url":null,"abstract":"Optimization at the early stages of design are crucial. However, due to an overwhelming number of design and optimization options, design exploration is often conducted in a qualitative, ad-hoc manner. This paper presents a methodology and interactive environment for guiding the exploration process. A prototype targeting behavioral-level optimization for datapath-intensive ASIC implementations has been developed. The key to the approach is encapsulated knowledge about the various optimizations and a set of techniques to automatically extract the \"essence\" of a design description. At each stage in the exploration process, the system suggests and ranks potential optimizations, both in terms of immediate and longer-term impact. It also provides evaluations of the design and of the likely affects each optimization will have on metrics like power and performance. In the new approach, the designer is responsible for making the actual optimization selections. However, using the provided guidance, designers can make decisions in a more informed manner, and therefore can explore the design solution space more effectively. The effectiveness of the approach is demonstrated on a number of designs.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128860580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Delay-optimal technology mapping by DAG covering DAG覆盖的延迟最优技术映射
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277142
Y. Kukimoto, R. Brayton, Prashant S. Sawkar
{"title":"Delay-optimal technology mapping by DAG covering","authors":"Y. Kukimoto, R. Brayton, Prashant S. Sawkar","doi":"10.1145/277044.277142","DOIUrl":"https://doi.org/10.1145/277044.277142","url":null,"abstract":"We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs. Experimental results demonstrate that significant delay improvement is possible by this new approach.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121411880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 91
An optimization-based error calculation for statistical power estimation of CMOS logic circuits 基于优化的CMOS逻辑电路统计功率估计误差计算
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724559
Byunggyu Kwak, E. Park
{"title":"An optimization-based error calculation for statistical power estimation of CMOS logic circuits","authors":"Byunggyu Kwak, E. Park","doi":"10.1109/DAC.1998.724559","DOIUrl":"https://doi.org/10.1109/DAC.1998.724559","url":null,"abstract":"We present a statistical power estimation method where the estimation time and accuracy can be balanced by assigning smaller errors to the nodes with higher power dissipation and higher errors to the nodes with lower power dissipation. To calculate the error rates for individual nodes, a quadratic programming based problem is formulated which incorporates the distribution data of all individual node switching activities. Also, an iterative statistical power estimation system is presented. Finally, we demonstrate experimental results which show drastic reduction in the number of simulation patterns compared to previous methods.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126109701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Virtual chip: making functional models work on real target systems 虚拟芯片:使功能模型在真实目标系统上工作
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277084
Nam-Do Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, I. Park, C. Kyung
{"title":"Virtual chip: making functional models work on real target systems","authors":"Nam-Do Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, I. Park, C. Kyung","doi":"10.1145/277044.277084","DOIUrl":"https://doi.org/10.1145/277044.277084","url":null,"abstract":"As design complexity increases, functional verification becomes a crucial issue to ensure design correctness at an early design stage. Traditional methods for verifying functional designs are based on the HDL simulation, which is becoming the bottleneck of the design cycle because of the increasing design complexity. The accurate verification ability at the architectural level through a large set of the test programs and real world applications is a foundation for the next design step. In this paper, we describe how to verify a functional model on a real target system. The proposed methodology called virtual chip makes it possible not only to check the functional correctness on real systems, but also to explore design space by measuring the performance effectiveness of various architecture parameters under real applications. Experimental results show that functional models can be verified on real systems using complicated application programs. The proposed functional verification method is faster than HDL simulation and even comparable to emulation.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126659518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A fast sequential learning technique for real circuits with application to enhancing ATPG performance 一种用于实际电路的快速顺序学习技术，用于提高ATPG性能
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277206
A. El-Maleh, M. Kassab, J. Rajski
{"title":"A fast sequential learning technique for real circuits with application to enhancing ATPG performance","authors":"A. El-Maleh, M. Kassab, J. Rajski","doi":"10.1145/277044.277206","DOIUrl":"https://doi.org/10.1145/277044.277206","url":null,"abstract":"This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124984048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Generic global placement and floorplanning 通用的全局布局和地板规划
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277119
H. Eisenmann, F. Johannes
{"title":"Generic global placement and floorplanning","authors":"H. Eisenmann, F. Johannes","doi":"10.1145/277044.277119","DOIUrl":"https://doi.org/10.1145/277044.277119","url":null,"abstract":"We present a new force directed method for global placement. Besides the well-known wire length dependent forces we use additional forces to reduce cell overlaps and to consider the placement area. Compared to existing approaches, the main advantage is that the algorithm provides increased flexibility and enables a variety of demanding applications. Our algorithm is capable of addressing the problems of global placement, floorplanning, timing minimization and interaction to logic synthesis. Among the considered objective functions are area, timing, congestion and heat distribution. The iterative nature of the algorithm assures that timing requirements are precisely met. While showing similar CPU time requirements it outperforms Gordian by an average of 6 percent and TimberWolf by an average of 8 percent in wire length and yields significantly better timing results.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125623468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 386
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