利用电压缩放技术的超低功耗MPEG4编解码器核心设计方法

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI:10.1145/277044.277178

K. Usami, M. Igarashi, T. Ishikawa, M. Kanazawa, Masafumi Takahashi, M. Hamada, H. Arakida, T. Terazawa, T. Kuroda

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引用次数: 67

摘要

本文描述了一种完全自动化的低功耗设计方法，其中三种不同的电压缩放技术结合在一起。在保持性能的同时，电源电压具有全局、选择性和自适应缩放。这种方法使我们能够在三周的周转时间内设计出比原来功耗低58%的MPEG4编解码器核心。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

This paper describes a fully automated low-power design methodology in which three different voltage-scaling techniques are combined together. Supply voltage is scaled globally, selectively, and adaptively while keeping the performance. This methodology enabled us to design an MPEG4 codec core with 58% less power than the original in three week turn-around-time.

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Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

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