一种用于实际电路的快速顺序学习技术，用于提高ATPG性能

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI:10.1145/277044.277206

A. El-Maleh, M. Kassab, J. Rajski

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引用次数: 11

摘要

本文提出了一种高效、新颖的隐含、无效状态和束缚门序贯学习方法。它可以处理真实的工业电路，具有多个时钟域和部分设置/复位。该方法通过提高故障覆盖率和减少测试生成次数来提高序列ATPG的效率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A fast sequential learning technique for real circuits with application to enhancing ATPG performance

This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times.

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Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

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