System-chip test strategies

Abstract

A major challenge in realizing core-based system-chips is the adoption of adequate test and diagnosis strategies. This paper focuses on the current industrial practices in test strategies for system-chips. It discusses the challenges in testing embedded cores, the testing requirements for individual cores, and their test access mechanisms. It also covers the integrated test strategies for system-chips based on reusable cores. In addition to the state-of-the-art practices in testability schemes, this paper covers the current standardization efforts for embedded core test interface mechanisms.