2019 22nd Euromicro Conference on Digital System Design (DSD)最新文献_第3页

Local Monitoring of Embedded Applications and Devices using Artificial Neural Networks 使用人工神经网络的嵌入式应用和设备的本地监控

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00076

F. Bahnsen, Goerschwin Fey

引用次数: 2

Toward a Hardware Man-in-the-Middle Attack on PCIe Bus for Smart Data Replay 基于PCIe总线的智能数据重放硬件中间人攻击研究

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00042

Mohamed Amine Khelif, J. Lorandel, O. Romain, Matthieu Regnery, Denis Baheux, G. Barbu

{"title":"Toward a Hardware Man-in-the-Middle Attack on PCIe Bus for Smart Data Replay","authors":"Mohamed Amine Khelif, J. Lorandel, O. Romain, Matthieu Regnery, Denis Baheux, G. Barbu","doi":"10.1109/DSD.2019.00042","DOIUrl":"https://doi.org/10.1109/DSD.2019.00042","url":null,"abstract":"The growing need for speed of recent embedded systems leads to the adoption of the high speed communication PCIe protocol (Peripheral Component Interconnect Express) as an internal data bus. This technology is used in some recent smartphones, and will be probably adopted by the others in the next few years. The communication between the SoC and its memory through the PCIe bus represent an important source of information for criminal investigations. In this paper, we present a new reliable attack vector on PCIe. We chose to perform a hardware Man-in-the-Middle attack, allowing real-time data analysis, data-replay and a copy technique inspired by the shadow-copy principle. Through this attack, we will be able to locate, duplicate and replay sensitive data. The main challenge of this article is to develop an architecture compliant with PCIe protocol constraints such as response time, frequency and throughput, in order to be invisible to the communication parts. We designed a proof of concept of an emulator based on a computer with PCIe 3.0 bus and a Stratix 5 FPGA with an endpoint PCIe port as development target.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125117180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Publisher's Information 出版商的信息

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/dsd.2019.00110

引用次数: 0

Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent 基于AES和Serpent的动态逻辑重构侧信道保护

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00048

Petr Socha, Jan Brejník, Stanislav Jerabek, M. Novotný, N. Mentens

{"title":"Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent","authors":"Petr Socha, Jan Brejník, Stanislav Jerabek, M. Novotný, N. Mentens","doi":"10.1109/DSD.2019.00048","DOIUrl":"https://doi.org/10.1109/DSD.2019.00048","url":null,"abstract":"Dynamic logic reconfiguration is a concept which allows for efficient on-the-fly modifications of combinational circuit behaviour in both ASIC and FPGA devices. The reconfiguration of Boolean functions is achieved by modification of their generators (e.g. shift register-based look-up tables) and it can be controlled from within the chip, without the necessity of any external intervention. This hardware polymorphism can be utilized for the implementation of side-channel attack countermeasures, as demonstrated by Sasdrich et al. for the lightweight cipher PRESENT. In this work we adopt these countermeasures to two of the AES finalists, namely Rijndael and Serpent. Just like PRESENT, both Rijndael and Serpent are block ciphers based on a substitution-permutation network. We describe the countermeasures and adjustments necessary to protect these ciphers using the resources available in modern Xilinx FPGAs. We describe our VHDL implementations and evaluate the side-channel leakage and effectiveness of different countermeasure combinations using a methodology based on Welch's t-test. We did not detect any significant leakage from the fully protected versions of our implementations. We show that the countermeasures proposed by Sasdrich et al. are, with some modifications compared to the protected PRESENT implementation, successfully applicable to AES and Serpent.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133690782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

MARM-GA: Mapping Applications to Reconfigurable Mesh using Genetic Algorithm MARM-GA:基于遗传算法的可重构网格映射应用

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00013

P. Kullu, S. Tosun

{"title":"MARM-GA: Mapping Applications to Reconfigurable Mesh using Genetic Algorithm","authors":"P. Kullu, S. Tosun","doi":"10.1109/DSD.2019.00013","DOIUrl":"https://doi.org/10.1109/DSD.2019.00013","url":null,"abstract":"Rapidly decreasing size of the CMOS transistors allowed us to place more components on a single chip than ever before. In order to meet the performance demands of these dense designs, designers introduced an efficient communication paradigm, Network-on-Chip (NoC), instead of traditional wiring-based methods. Although mesh topology is most commonly used topology for NoC design, it has several problems such as network congestion and energy consumption. Reconfigurable mesh topology is a good alternative to traditional mesh since it gives more mapping and routing options for reducing network congestion. However, design automation tools still lack efficient mapping and routing algorithms for reconfigurable meshes. In this study, we propose a genetic algorithm (GA) based method that simultaneously maps the application nodes on 2D reconfigurable mesh structure and determines the routing paths between communicating pairs with the objective of energy minimization. We have applied our method on four benchmarks and compared our results against two heuristic strategies. Simulation results show the superiority of our proposed method over the existing ones in terms of energy consumption.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116648549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

[Title page i] [标题页i]

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/dsd.2019.00001

引用次数: 0

True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits 用于数字电路可测试性分析的结构合成bdd真路径跟踪

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00077

R. Ubar, L. Jürimägi, A. O. Adekoya, M. Jenihhin

{"title":"True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits","authors":"R. Ubar, L. Jürimägi, A. O. Adekoya, M. Jenihhin","doi":"10.1109/DSD.2019.00077","DOIUrl":"https://doi.org/10.1109/DSD.2019.00077","url":null,"abstract":"A method is proposed for testability analysis of digital circuits focusing on calculating the probabilistic controllability measures in terms of signal probabilities, when random or pseudorandom patterns are applied to the circuit inputs. The tasks of calculating the probabilistic observability and testability measures are transformed into the task of calculating the controllability. The structure of the circuit is presented as a set of Structurally Synthesized BDDs (SSBDD), which allows controllability analysis with higher speed than carrying out calculations on the gate-level, retaining the possibilities of assessment of the controllability of all gate-level nodes represented by related SSBDD nodes. The proposed method is based on tracing true paths in SSBDDs. A general case is considered, where the circuit may include redundancies. It is shown that the known methods of calculating signal probabilities, which are not taking into account the redundancy in circuits, are not accurate. A method is proposed for proving the redundancy of faults, which is based on the same idea of SSBDD path tracing. Experimental results show higher accuracy and higher speed of SSBDD-based probability calculations, compared to gate-level calculation.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133327686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Accurate Inexact Calculations of Non-Homogeneous Markov Chains 非齐次马尔可夫链的精确非精确计算

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00074

J. Reznícek, Martin Kohlík, H. Kubátová

引用次数: 4

Design and Verification of Secure Cache Wrapper Against Access-Driven Side-Channel Attacks 针对访问驱动的侧信道攻击的安全缓存包装器设计与验证

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00108

Behrad Niazmand, Siavoosh Payandeh Azad, G. Jervan, Martha Johanna Sepúlveda

{"title":"Design and Verification of Secure Cache Wrapper Against Access-Driven Side-Channel Attacks","authors":"Behrad Niazmand, Siavoosh Payandeh Azad, G. Jervan, Martha Johanna Sepúlveda","doi":"10.1109/DSD.2019.00108","DOIUrl":"https://doi.org/10.1109/DSD.2019.00108","url":null,"abstract":"While caches are shared resources used to speedup the execution of applications, including the execution of cryptographic applications, their use can expose the system to attacks. Access-driven is one of the most popular cache attacks. They have been demonstrated in different hardware platforms, from servers to smart phones, which even were operating in virtualized environments. Designing hardware solutions to protect against access-driven attacks is still a challenge. Moreover, the security verification of such solutions still needs further exploration. This paper presents two main contributions. First, we propose a generic hardware wrapper able to protect caches against accessdriven cache attacks, based on an address translation policy to obfuscate the cache accesses. Second, we use an extended version of a previously proposed formal method to verify the security of cache against such attacks, by means of properties. Experimental results show the effectiveness of our hardware wrapper against access-driven cache attacks along with formal proof, while incurring an average area overhead below 2% and a negligible critical path overhead.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"5 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126118625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

On Analyzing Memory Latency for Embedded CPS Platforms 嵌入式CPS平台的内存延迟分析

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00061

Selma Saidi

引用次数: 0