2019 22nd Euromicro Conference on Digital System Design (DSD)最新文献_第2页

Leveraging Domain Knowledge for the Efficient Design-Space Exploration of Advanced Cyber-Physical Systems 利用领域知识对先进的信息物理系统进行有效的设计空间探索

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00058

Yon Vanommeslaeghe, J. Denil, Jasper De Viaene, D. Ceulemans, S. Derammelaere, P. D. Meulenaere

{"title":"Leveraging Domain Knowledge for the Efficient Design-Space Exploration of Advanced Cyber-Physical Systems","authors":"Yon Vanommeslaeghe, J. Denil, Jasper De Viaene, D. Ceulemans, S. Derammelaere, P. D. Meulenaere","doi":"10.1109/DSD.2019.00058","DOIUrl":"https://doi.org/10.1109/DSD.2019.00058","url":null,"abstract":"Cyber-physical systems are becoming increasingly complex. In these advanced systems, the different engineering domains involved in the design process become more and more intertwined. In these situations, a traditional (sequential) design process becomes inefficient in finding good designs options. Instead, an integrated approach is needed where parameters in both the control and embedded domain can be chosen, evaluated and optimized to have a good solution in both domains. However, in such an approach, the combined design space becomes vast. As such, methods are needed to mitigate this problem. In this paper, we show how domain knowledge can be used to guide the design-space exploration process for an advanced control system and its deployment on embedded hardware. We use domain knowledge, captured in an ontology, to reason about the relationships between parameters in the different domains. This leads to a stepwise design space-exploration process where this domain knowledge is used to quickly reduce the design space to a subset of likely good candidates. In this process, we make use of cross-domain evaluation to find feasible design options with good system-level performance.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124456945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

SAT-Hard: A Learning-Based Hardware SAT-Solver SAT-Hard:一个基于学习的硬件sat求解器

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00021

B. Ustaoğlu, S. Huhn, F. Sill, Daniel Große, R. Drechsler

{"title":"SAT-Hard: A Learning-Based Hardware SAT-Solver","authors":"B. Ustaoğlu, S. Huhn, F. Sill, Daniel Große, R. Drechsler","doi":"10.1109/DSD.2019.00021","DOIUrl":"https://doi.org/10.1109/DSD.2019.00021","url":null,"abstract":"Within the last decades, tremendous research work has been carried out on the development of software-based algorithms to solve the Boolean Satisfiability Problem. These SAT-solvers have then been heavily orchestrated for addressing complex computational tasks like the verification of circuits. In this field, most of the applied techniques focused only on the design phase of the circuit. Due to this fact, new approaches have been published in the literature solely focusing on online verification as well as self-verification. These kind of solutions strictly require Hardware (HW) SAT-solvers that can be integrated into a system while introducing only low hardware overhead and still providing high flexibility. By following these observations, this work presents SAT-Hard: In contrast to the state-of-the-art, SAT-Hard takes advantage of learning techniques to support features like clause learning and non-chronological backtracking, and combines them within a lightweight and standalone HW device. By this, a run-time speed-up of 2,000x can be achieved. Furthermore, the experimental evaluation clearly demonstrates that those complex problems can be solved in less than 20 seconds. Particularly due to its compactness, SAT-Hard is suitable for self-verification that enables the continuous verification of an integrated system during its lifetime.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127364311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Bit-Shift-Based Accelerator for CNNs with Selectable Accuracy and Throughput 基于位偏移的CNNs加速器，具有可选择的精度和吞吐量

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00106

Sebastian Vogel, R. Raghunath, A. Guntoro, Kristof Van Laerhoven, G. Ascheid

{"title":"Bit-Shift-Based Accelerator for CNNs with Selectable Accuracy and Throughput","authors":"Sebastian Vogel, R. Raghunath, A. Guntoro, Kristof Van Laerhoven, G. Ascheid","doi":"10.1109/DSD.2019.00106","DOIUrl":"https://doi.org/10.1109/DSD.2019.00106","url":null,"abstract":"Hardware accelerators for compute intensive algorithms such as convolutional neural networks benefit from number representations with reduced precision. In this paper, we evaluate and extend a number representation based on power-of-two quantization enabling bit-shift-based processing of multiplications. We found that weights of a neural network can either be represented by a single 4 bit power-of-two value or with two 4 bit values depending on accuracy requirements. We evaluate the classification accuracy of VGG-16 and ResNet50 on the ImageNet dataset with weights represented in our novel number format. To include a more complex task, we additionally evaluate the format on two networks for semantic segmentation. In addition, we design a novel processing element based on bit-shifts which is configurable in terms of throughput (4 bit mode) and accuracy (8 bit mode). We evaluate this processing element in an FPGA implementation of a dedicated accelerator for neural networks incorporating a 32-by-64 processing array running at 250 MHz with 1 TOp/s peak throughput in 8 bit mode. The accelerator is capable of processing regular convolutional layers and dilated convolutions in combination with pooling and upsampling. For a semantic segmentation network with 108.5 GOp/frame, our FPGA implementation achieves a throughput of 7.0 FPS in the 8 bit accurate mode and upto 11.2 FPS in the 4 bit mode corresponding to 760.1 GOp/s and 1,218 GOp/s effective throughput, respectively. Finally, we compare the novel design to classical multiplier-based approaches in terms of FPGA utilization and power consumption. Our novel multiply-accumulate engines designed for the optimized number representation uses 9 % less logical elements while allowing double throughput compared to a classical implementation. Moreover, a measurement shows 25 % reduction of power consumption at same throughput. Therefore, our flexible design offers a solution to the trade-off between energy efficiency, accuracy, and high throughput.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121404223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation 过程变化对最坏情况能耗估计的影响建模

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00092

David Trilla, Carles Hernández, J. Abella, F. Cazorla

引用次数: 1

Reliability Assessment of Flooded Min-Sum LDPC Decoders Based on Sub-Threshold Processing Units 基于子阈值处理单元的泛洪最小和LDPC译码器可靠性评估

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00096

S. Nimara

引用次数: 0

Combinational Decompressors with Nonlinear Codes 非线性码组合减压器

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00078

O. Novák, M. Rozkovec, Jan Plíva

引用次数: 1

Local Monitoring of Embedded Applications and Devices using Artificial Neural Networks 使用人工神经网络的嵌入式应用和设备的本地监控

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00076

F. Bahnsen, Goerschwin Fey

引用次数: 2

Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent 基于AES和Serpent的动态逻辑重构侧信道保护

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00048

Petr Socha, Jan Brejník, Stanislav Jerabek, M. Novotný, N. Mentens

{"title":"Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent","authors":"Petr Socha, Jan Brejník, Stanislav Jerabek, M. Novotný, N. Mentens","doi":"10.1109/DSD.2019.00048","DOIUrl":"https://doi.org/10.1109/DSD.2019.00048","url":null,"abstract":"Dynamic logic reconfiguration is a concept which allows for efficient on-the-fly modifications of combinational circuit behaviour in both ASIC and FPGA devices. The reconfiguration of Boolean functions is achieved by modification of their generators (e.g. shift register-based look-up tables) and it can be controlled from within the chip, without the necessity of any external intervention. This hardware polymorphism can be utilized for the implementation of side-channel attack countermeasures, as demonstrated by Sasdrich et al. for the lightweight cipher PRESENT. In this work we adopt these countermeasures to two of the AES finalists, namely Rijndael and Serpent. Just like PRESENT, both Rijndael and Serpent are block ciphers based on a substitution-permutation network. We describe the countermeasures and adjustments necessary to protect these ciphers using the resources available in modern Xilinx FPGAs. We describe our VHDL implementations and evaluate the side-channel leakage and effectiveness of different countermeasure combinations using a methodology based on Welch's t-test. We did not detect any significant leakage from the fully protected versions of our implementations. We show that the countermeasures proposed by Sasdrich et al. are, with some modifications compared to the protected PRESENT implementation, successfully applicable to AES and Serpent.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133690782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

MARM-GA: Mapping Applications to Reconfigurable Mesh using Genetic Algorithm MARM-GA:基于遗传算法的可重构网格映射应用

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00013

P. Kullu, S. Tosun

{"title":"MARM-GA: Mapping Applications to Reconfigurable Mesh using Genetic Algorithm","authors":"P. Kullu, S. Tosun","doi":"10.1109/DSD.2019.00013","DOIUrl":"https://doi.org/10.1109/DSD.2019.00013","url":null,"abstract":"Rapidly decreasing size of the CMOS transistors allowed us to place more components on a single chip than ever before. In order to meet the performance demands of these dense designs, designers introduced an efficient communication paradigm, Network-on-Chip (NoC), instead of traditional wiring-based methods. Although mesh topology is most commonly used topology for NoC design, it has several problems such as network congestion and energy consumption. Reconfigurable mesh topology is a good alternative to traditional mesh since it gives more mapping and routing options for reducing network congestion. However, design automation tools still lack efficient mapping and routing algorithms for reconfigurable meshes. In this study, we propose a genetic algorithm (GA) based method that simultaneously maps the application nodes on 2D reconfigurable mesh structure and determines the routing paths between communicating pairs with the objective of energy minimization. We have applied our method on four benchmarks and compared our results against two heuristic strategies. Simulation results show the superiority of our proposed method over the existing ones in terms of energy consumption.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116648549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education dsd - 1:面向数字系统设计教育的混合功能开发板

2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00032

Anastasios Fanariotis, T. Orphanoudakis, V. Fotopoulos, P. Kitsos

{"title":"DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education","authors":"Anastasios Fanariotis, T. Orphanoudakis, V. Fotopoulos, P. Kitsos","doi":"10.1109/DSD.2019.00032","DOIUrl":"https://doi.org/10.1109/DSD.2019.00032","url":null,"abstract":"The present paper describes the design and implementation of a development board, designed in Digital Systems and Media Computing Laboratory of the Hellenic Open University which is very active in the field of digital systems design. The board hosts an MCU and an FPGA on the same PCB, cooperating with tight interconnection between them and supported by a set of basic on-board peripherals that cover some of the most essential educational examples in the field, minimizing the need for external devices. The design is geared i) towards ease of use in order to alleviate any initial setup stress by students or inexperienced designers and ii) towards low-cost fabrication in order to facilitate educational institutions who provide distance education to offer this board to every student for out-of-laboratory usage. The design process, consists of three main stages; the PCB design, the firmware development and the lastly the host computer software development. The architectural and design choices made for each stage are described fully later on the paper with each decision balancing between ease-of-use, cost and functionality, in the form of offered services. The board functions as a very low-cost laboratory educational platform for both low level HDL training as well as higher level MCU Firmware programming, supporting even more complex scenarios of FPGA softcore usage and programming or concurrent usage of FPGA and MCU in complete System-on-Chip (SoC) designs.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124528516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0