基于位偏移的CNNs加速器,具有可选择的精度和吞吐量

Sebastian Vogel, R. Raghunath, A. Guntoro, Kristof Van Laerhoven, G. Ascheid
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引用次数: 3

摘要

用于计算密集型算法(如卷积神经网络)的硬件加速器受益于精度降低的数字表示。在本文中,我们评估并扩展了一种基于2次幂量化的数字表示,使得基于位移位的乘法处理成为可能。我们发现,根据精度要求,神经网络的权重既可以用单个4位的2次幂值表示,也可以用两个4位值表示。我们评估了VGG-16和ResNet50在ImageNet数据集上的分类精度,权重用我们的新数字格式表示。为了包括一个更复杂的任务,我们还在两个网络上评估了语义分割的格式。此外,我们设计了一种基于位移位的新型处理元件,可在吞吐量(4位模式)和精度(8位模式)方面进行配置。我们在神经网络专用加速器的FPGA实现中评估了该处理元件,该加速器包含一个运行在250 MHz的32 × 64处理阵列,在8位模式下具有1 TOp/s峰值吞吐量。该加速器能够结合池化和上采样处理规则卷积层和扩展卷积。对于108.5 GOp/帧的语义分割网络,我们的FPGA实现在8位精确模式下实现了7.0 FPS的吞吐量,在4位模式下达到11.2 FPS,分别对应760.1 GOp/s和1218 GOp/s的有效吞吐量。最后,我们在FPGA利用率和功耗方面将新设计与基于乘法器的经典方法进行了比较。我们为优化的数字表示而设计的新型乘法累加引擎使用的逻辑元素比传统实现少9%,同时允许双倍的吞吐量。此外,一项测量表明,在相同的吞吐量下,功耗降低了25%。因此,我们灵活的设计为能源效率,精度和高吞吐量之间的权衡提供了解决方案。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Bit-Shift-Based Accelerator for CNNs with Selectable Accuracy and Throughput
Hardware accelerators for compute intensive algorithms such as convolutional neural networks benefit from number representations with reduced precision. In this paper, we evaluate and extend a number representation based on power-of-two quantization enabling bit-shift-based processing of multiplications. We found that weights of a neural network can either be represented by a single 4 bit power-of-two value or with two 4 bit values depending on accuracy requirements. We evaluate the classification accuracy of VGG-16 and ResNet50 on the ImageNet dataset with weights represented in our novel number format. To include a more complex task, we additionally evaluate the format on two networks for semantic segmentation. In addition, we design a novel processing element based on bit-shifts which is configurable in terms of throughput (4 bit mode) and accuracy (8 bit mode). We evaluate this processing element in an FPGA implementation of a dedicated accelerator for neural networks incorporating a 32-by-64 processing array running at 250 MHz with 1 TOp/s peak throughput in 8 bit mode. The accelerator is capable of processing regular convolutional layers and dilated convolutions in combination with pooling and upsampling. For a semantic segmentation network with 108.5 GOp/frame, our FPGA implementation achieves a throughput of 7.0 FPS in the 8 bit accurate mode and upto 11.2 FPS in the 4 bit mode corresponding to 760.1 GOp/s and 1,218 GOp/s effective throughput, respectively. Finally, we compare the novel design to classical multiplier-based approaches in terms of FPGA utilization and power consumption. Our novel multiply-accumulate engines designed for the optimized number representation uses 9 % less logical elements while allowing double throughput compared to a classical implementation. Moreover, a measurement shows 25 % reduction of power consumption at same throughput. Therefore, our flexible design offers a solution to the trade-off between energy efficiency, accuracy, and high throughput.
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