Reliability Assessment of Flooded Min-Sum LDPC Decoders Based on Sub-Threshold Processing Units

Abstract

This paper aims to evaluate the performance degradation of faulty flooded Min-Sum LDPC decoder architectures based on sub-threshold processing units, by performing hierarchical decomposition of combinational and sequential sub-blocks of processing units described at RTL level. Logic synthesis of the combinational sub-blocks is performed and faults are injected for each logic gate according to a delay-dependent fault model for critical and non-critical paths of the design. The impact of the probabilistic behavior of sub-threshold gates on the error-correction performance of the decoder is analyzed in terms of bit error rate (BER) metrics for Binary Additive White Gaussian Noise (BiAWGN) communication channel model.