On Analyzing Memory Latency for Embedded CPS Platforms

Abstract

The current trend towards automation and connectivity is driving the increased adoption of complex and parallel computational embedded multiprocessors platforms in CPS. These platforms are characterized by a tightly-coupled shared memory system. Data storage and access have then a significant impact on performance and need to be carefully considered to comply with stringent timing constraints often required by CPS. However, verifying such timing requirements becomes more and more challenging due to the increasing complexity of the underlying memory system thereby leading to non-deterministic access latencies. In this paper we present some of the features that need to be considered when bounding shared memory latency in complex systems and discuss how standard system performance analysis methods can be enhanced to consider specific shared-memory hardware and software features like address mapping, locality of accesses and requests interleaving.