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2019 22nd Euromicro Conference on Digital System Design (DSD)最新文献

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Deep Learning Side-Channel Attack Against Hardware Implementations of AES 针对AES硬件实现的深度学习侧信道攻击
2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00046
Takaya Kubota, Kota Yoshida, M. Shiozaki, T. Fujino
{"title":"Deep Learning Side-Channel Attack Against Hardware Implementations of AES","authors":"Takaya Kubota, Kota Yoshida, M. Shiozaki, T. Fujino","doi":"10.1109/DSD.2019.00046","DOIUrl":"https://doi.org/10.1109/DSD.2019.00046","url":null,"abstract":"In the field of image recognition, machine learning technologies, especially deep learning, have been rapidly advancing alongside with the advances of hardware such as GPUs. In image recognition, in general, large numbers of labeled sets containing image and correct value pairs to be identified are input to a neural network, and repeatedly learning the set enables the neural network to identify objects with high accuracy. A new side-channel attack method, deep learning side-channel attack (DLSCA), utilizes the high identifying ability of the neural network to try and unveil a secret key of the cryptographic module by being trained with power waveforms and learning the leak model. However, at this stage, attacks on software implementations have been mainly investigated. In contrast, there are few studies about hardware implementations especially such as ASIC circuits. In this paper, we investigate the use of DL-SCA against hardware implementations of AES and demonstrate that it is able to unveil the secret key by applying a new technique named \"mixed model dataset based on round-round XORed value.\" We also compare the attack performance and characteristics of DL-SCA with conventional analysis methods such as correlation power analysis and conventional template attack.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131366709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Graphical Model Transformation Analysis for Cognitive Computing and Machine Learning on the SpiNNaker Chip Multiprocessor SpiNNaker芯片多处理器认知计算和机器学习的图形模型转换分析
2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00112
A. Andreou, Daniel R. Mendat
{"title":"Graphical Model Transformation Analysis for Cognitive Computing and Machine Learning on the SpiNNaker Chip Multiprocessor","authors":"A. Andreou, Daniel R. Mendat","doi":"10.1109/DSD.2019.00112","DOIUrl":"https://doi.org/10.1109/DSD.2019.00112","url":null,"abstract":"The SpiNNaker is a parallel neuromorphic hardware architecture that enables a wide variety of computations to be performed in a distributed, event-based manner. The authors have previously shown large speedups for performing MCMC inference using spiking neurons on the SpiNNaker as well as the Parallella, an open-source parallel computing device. Both architectures provide platforms for performing innovative low-power computations, and there are other massively parallel chip multiprocessor platforms arriving in the future. This paper explores a complexity analysis for the algorithms in the automated framework developed to take a binary Bayesian network the whole way from reading in its text file description and transforming the network for parallel MCMC sampling to performing sampling on the SpiNNaker. Although it is focused on the SpiNNaker, many of these principles apply when using other neuromorphic chip multiprocessors, as this algorithmic flow has already been used with the Parallella after some modifications.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132327815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Hardware Accelerator for Edge Detection in High-Definition Video using Cellular Neural Networks 基于细胞神经网络的高清视频边缘检测硬件加速器
2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00017
Ignacio Pérez, Wladimir E. Valenzuela, M. Figueroa
{"title":"A Hardware Accelerator for Edge Detection in High-Definition Video using Cellular Neural Networks","authors":"Ignacio Pérez, Wladimir E. Valenzuela, M. Figueroa","doi":"10.1109/DSD.2019.00017","DOIUrl":"https://doi.org/10.1109/DSD.2019.00017","url":null,"abstract":"This paper presents the architecture of a hardware accelerator for a cellular neural network (CeNN) with an application to real-time edge detection on visible-range and infrared video. The accelerator features fully-pipelined processing elements (PEs) that exploit the data parallelism in the algorithm to perform an iteration of the CeNN on a stream of video data with high throughput. The memory architecture exploits the locality of reference in the CeNN, so that each PE uses only 5 line buffers to store pixel, state, and output data, thus achieving low on-chip memory utilization. Implemented on a Xilinx XC7A200T FPGA running at 245MHz, the accelerator performs edge detection on 1080p video using a single CeNN iteration with a throughput of 118 frames per second (fps), a total latency of 15.7us, and 618mW of power consumption. The architecture features static reconfiguration to store built-in kernels and to add more PEs to support multiple iterations of the CeNN algorithm. More kernels can be added dynamically through a serial interface.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133268042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On Precise Fault Localization and Identification in NoC Architectures NoC体系结构故障的精确定位与识别
2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00075
M. Stáva
{"title":"On Precise Fault Localization and Identification in NoC Architectures","authors":"M. Stáva","doi":"10.1109/DSD.2019.00075","DOIUrl":"https://doi.org/10.1109/DSD.2019.00075","url":null,"abstract":"For network-on-chip (NoC), this paper presents a novel online fault-tolerance method based on precise fault localization and identification. We introduce a concept of distinguishing between intra-switch path faults, a concept of retransmission credit as a method of distinguishing between permanent and transient faults, and a concept of long transient recovery timeout as a method of distinguishing between short and long (or burst of) transient faults. Another concept of monitoring errors separately on links and switches is also employed. The fault-tolerance concepts introduced bring the higher performance of NoCs in comparison to existing error recovery schemes. Experimental results show the performance and resource utilization of the proposed NoC error recovery scheme.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131351810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study 多维Pareto边界交集确定与处理器优化案例研究
2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00091
Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomás Hruska, Z. Kotásek
{"title":"Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study","authors":"Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomás Hruska, Z. Kotásek","doi":"10.1109/DSD.2019.00091","DOIUrl":"https://doi.org/10.1109/DSD.2019.00091","url":null,"abstract":"Almost all today's electronic devices are equipped with a processor. Different applications require and depend on different properties of the processor. For example, the fast growing field of Internet of Things depends on a long operation time of the devices when powered with batteries. Using general purpose processors has proved ineffective which led to a growing usage of Application-Specific Instruction-Set processors (ASIPs) which can be optimized for specific applications using different modifications of their properties (such as the number of registers, cache sizes, instruction set modifications, etc.). A suitable processor configuration can be hand-picked by a designer or by an automatic tool.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128311514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Authenticated Encryption Schemes on Java Card Java卡上的认证加密方案
2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00043
R. Pal
{"title":"Authenticated Encryption Schemes on Java Card","authors":"R. Pal","doi":"10.1109/DSD.2019.00043","DOIUrl":"https://doi.org/10.1109/DSD.2019.00043","url":null,"abstract":"Authenticated encryption algorithms will be the main workhorse for secret-key cryptography in the future. The ever increasing use of smart cards requires that authenticated encryption schemes are also available on smart cards. In this paper, five authenticated ciphers from the CAESAR competition are implemented and evaluated on Java card platform. The performance and memory footprint are determined for each cipher which is relevant to low compute-power, memory-constrained embedded devices. This work enables availability of authenticated ciphers on Java card. The paper also motivates the case for providing authenticated encryption on cryptographic co-processors of smart cards.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128405293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of CCOs with Implantable MEMS Pressure Sensors for Cardiovascular Applications 心血管应用可植入MEMS压力传感器CCOs的优化
2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00071
J. Miguel, Y. Lechuga, M. A. Allende, Mar Martínez
{"title":"Optimization of CCOs with Implantable MEMS Pressure Sensors for Cardiovascular Applications","authors":"J. Miguel, Y. Lechuga, M. A. Allende, Mar Martínez","doi":"10.1109/DSD.2019.00071","DOIUrl":"https://doi.org/10.1109/DSD.2019.00071","url":null,"abstract":"Implantable biomedical devices for telemonitoring Cardiovascular Diseases (CVD) generally comprise MEMS-type sensors used to acquire physiological signals, as well as CMOS electronics to perform powering, signal conditioning and data transmission. This work targets the optimization of several Capacitor-Controlled Oscillator (CCO) topologies for implantable applications, based on the analysis of their most relevant performance parameters. Comprehensive simulations allowed the estimation of the output frequency, percentage tuning range, maximum linearity error, phase noise and power consumption for each design. These performance metrics have been used to obtain the Figure of Merit for every CCO, showing a better overall response from single-ended ring topologies symmetrically loaded. However, the robustness of differential topologies against supply and substrate noise, and the voltage tuning range of sawtooth CCOs, increase their potential usage for implantable applications.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116765295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior 一种检测测试过程中功率峰值并打破系统病态行为的方法
2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00083
David Trilla, Carles Hernández, J. Abella, F. Cazorla
{"title":"An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior","authors":"David Trilla, Carles Hernández, J. Abella, F. Cazorla","doi":"10.1109/DSD.2019.00083","DOIUrl":"https://doi.org/10.1109/DSD.2019.00083","url":null,"abstract":"The verification and validation process of embedded critical systems requires providing evidence of their functional correctness and also that their non-functional behavior stays within limits. In this work, we focus on power peaks, which may cause voltage droops and thus, challenge performance to preserve correct operation upon droops. In this line, the use of complex software and hardware in critical embedded systems jeopardizes the confidence that can be placed on the tests carried out during the campaigns performed at analysis. This is so because it is unknown whether tests have triggered the highest power peaks that can occur during operation and whether any such peak can occur systematically. In this paper we propose the use of randomization, already used for timing analysis of real-time systems, as an enabler to guarantee that (1) tests expose those peaks that can arise during operation and (2) peaks cannot occur systematically inadvertently.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122076207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
[Copyright notice] (版权)
2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/dsd.2019.00003
{"title":"[Copyright notice]","authors":"","doi":"10.1109/dsd.2019.00003","DOIUrl":"https://doi.org/10.1109/dsd.2019.00003","url":null,"abstract":"","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125917328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes 基于systemc的虚拟原型的可扩展仿真验证
2019 22nd Euromicro Conference on Digital System Design (DSD) Pub Date : 2019-08-01 DOI: 10.1109/DSD.2019.00081
Mehran Goli, R. Drechsler
{"title":"Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes","authors":"Mehran Goli, R. Drechsler","doi":"10.1109/DSD.2019.00081","DOIUrl":"https://doi.org/10.1109/DSD.2019.00081","url":null,"abstract":"Virtual Prototypes (VPs) at the Electronic System Level (ESL) written in SystemC language using its Transaction Level Modeling (TLM) framework are increasingly adopted by the semiconductor industry. The main reason is that VPs are much earlier available, and their simulation is orders of magnitude faster in comparison to the hardware models implemented at lower levels of abstraction (e.g. RTL). This leads designers to use VPs as reference models for an early design verification. Hence, the correctness assurance of these reference models (VPs) is critical as undetected faults may propagate to less abstract levels in the design process, increasing the fixing cost and effort. In this paper, we propose a novel simulation-based verification approach to automatically validate the simulation behavior of a given SystemC VP against both the TLM-2.0 rules and its specifications (i.e. functional and timing behavior of communications in the VP). The scalability and the efficiency of the proposed approach are demonstrated using an extensive set of experiments including a real-word VP.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125058965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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