{"title":"Consideration of Security Attacks in the Design Space Exploration of Embedded Systems","authors":"Lukas Gressl, C. Steger, U. Neffe","doi":"10.1109/DSD.2019.00082","DOIUrl":"https://doi.org/10.1109/DSD.2019.00082","url":null,"abstract":"Designing secure systems is a complex task, particularly for designers who are no security experts. Cyber security plays a key role in embedded systems, especially for the domain of the Internet of Things (IoT). IoT systems of this kind are becoming increasingly important in daily life as they simplify various tasks. They are usually small, either embedded into bigger systems or battery driven, and perform monitoring or one shot tasks. Thus, they are subject to manifold constraints in terms of performance, power consumption, chip area, etc. As they are continuously connected to the internet and utilize our private data to perform their tasks, they are interesting for potential attackers. Cyber security thus plays an important role for the design of an IoT system. As the usage of security measures usually increases both computation time, as well as power consumption, a conflict between these constraints must be solved. For the designers of such systems, balancing these constraints constitutes a highly complex task. In this paper we propose a novel approach for considering possible security attacks on embedded systems, simplifying the consideration of security requirements immediately at the start of the design process. We introduce a security aware design space exploration framework which based on an architectural, behavioral and security attack description, finds the optimal design for IoT systems. We also demonstrate the feasibility and the benefits of our framework based on a door access system use case.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126175405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The European H2020 project VESSEDIA (Verification Engineering of Safety and SEcurity critical Dynamic Industrial Applications)","authors":"A. Puccetti","doi":"10.1109/DSD.2019.00089","DOIUrl":"https://doi.org/10.1109/DSD.2019.00089","url":null,"abstract":"This paper presents an overview of the H2020 project VESSEDIA [9] aimed at verifying the security and safety of modern connected systems also called IoT. The originality relies in using Formal Methods inherited from high-criticality applications domains to analyze the source code at different levels of intensity, to gather possible faults and weaknesses. The analysis methods are mostly exhaustive an guarantee that, after analysis, the source code of the application is error-free. This paper is structured as follows: after an introductory section 1 giving some factual data, section 2 presents the aims and the problems addressed; section 3 describes the project's use-cases and section 4 describes the proposed approach for solving these problems and the results achieved until now; finally, section 5 discusses some remaining future work.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128859453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Exploiting Emerging Reconfigurable Technologies for Secure Devices","authors":"Ansh Rupani, Shubham Rai, Akash Kumar","doi":"10.1109/DSD.2019.00107","DOIUrl":"https://doi.org/10.1109/DSD.2019.00107","url":null,"abstract":"In the present work, we show how new and emerging reconfigurable technologies provide promising improvement over CMOS in the field of hardware security and encryption. We demonstrate how security features are a natural outcome of the circuits based on Silicon Nanowire reconfigurable transistors. This forms the basis of authentication key based security technique. Using the authentication key based system, we obtained the maximum possible key-length for MCNC benchmark circuits. Further, we formulated security as a tunable aspect for a circuit, by introducing don't care adjustment. A combination of the above two is used to establish security in terms of Shannon's entropy. We show that using the above concepts, Shannon's entropy increases for 99.1% benchmarks out of which maximum entropy is reached for 38.5% of all the benchmarks. We demonstrate these concepts using a case study for a 2-bit Ripple Carry Adder (RCA) based on SiNW RFETs and compare the design with its CMOS counterpart.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130010768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Conical-Fishbone Clock Tree: A Clock-Distribution Network for a Heterogeneous Chip Multiprocessor AI Chiplet","authors":"Tomas Figliolia, A. Andreou","doi":"10.1109/DSD.2019.00111","DOIUrl":"https://doi.org/10.1109/DSD.2019.00111","url":null,"abstract":"In this paper we present a clock tree network that is inspired by the shape of an inverted cone. Conical sections are created in the inverted cone, and each of these resulting rings is considered to be one of the many nets in a Fishbone clock tree. When a ring is excited at uniform intervals from the ring below, the symmetry in the circular characteristics of the wire will make the effect of reflections be exactly the same along any place in the wire. The proposed clock tree named Conical-Fishbone clock tree allows ultra-low clock skew while offering the modularity to support a hierarchical design using standard CAD flows. The Conical-Fishbone tree network is employed in the L1- NOC, the L2-NOC and the DDR DRAM PHY of the core (17.47 mm X 14.13 mm) “chiplet” in the 2.5D nano-Abacus SOC currently being fabricated in the Global Foundries 55nm CMOS technology.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117272870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Device Driver and System Call Isolation in Embedded Devices","authors":"Maja Malenko, M. Baunach","doi":"10.1109/DSD.2019.00049","DOIUrl":"https://doi.org/10.1109/DSD.2019.00049","url":null,"abstract":"The number of low-end embedded devices in today's Internet of Things and Cyber-Physical Systems is increasing along with their security concerns. Memory isolation mechanisms are often absent, programming flaws lead to malfunctioning applications, which in turn can crush the whole system. A common design approach in these devices is to have applications, operating system components, and device driver libraries reside in a single non-isolated address space, which represents one vast attack surface. Furthermore, with increasing network connectivity and frequent dynamic updates, new or modified applications and services are uploaded, opening space for even more attacks. Isolating the execution of applications in these systems is still a challenge. In this work we provide a holistic hardware/software co-designed approach for memoryisolation, which prevents corruption of the state of the operating system and applications from a buggy software, including device drivers, interrupt service routines, and misused system calls. We implemented low-cost architectural extensions in a RISC-V-based microcontroller which work together with kernel-based protection concepts. Our evaluation shows that applications as well as the kernel can enjoy the benefits of the proposed memory isolation with minimal impact on performance and an insignificant increase in the area of the MCU.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122607190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-sensor Energy Efficient Obstacle Detection","authors":"Anupam Sobti, M. Balakrishnan, Chetan Arora","doi":"10.1109/DSD.2019.00014","DOIUrl":"https://doi.org/10.1109/DSD.2019.00014","url":null,"abstract":"With the improvement in technology, both the cost and the power requirement of cameras, as well as other sensors have come down significantly. It has allowed these sensors to be integrated into portable as well as wearable systems. Such systems are usually operated in a hands-free and always-on manner where they need to function continuously in a variety of scenarios. In such situations, relying on a single sensor or a fixed sensor combination can be detrimental to both performance as well as energy requirements. Consider the case of an obstacle detection task. Here using an RGB camera helps in recognizing the obstacle type but takes much more energy than an ultrasonic sensor. Infrared cameras can perform better than RGB camera at night but consume twice the energy. Therefore, an efficient system must use a combination of sensors, with an adaptive control that ensures the use of the sensors appropriate to the context. In this adaptation, one needs to consider both performance and energy and their trade-off. In this paper, we explore the strengths of different sensors as well their trade-off for developing a deep neural network based wearable device. We choose a specific case study in the context of a mobility assistance device for the visually impaired. The device detects obstacles in the path of a visually impaired person and is required to operate both at day and night with minimal energy to increase the usage time on a single charge. The device employs multiple sensors: ultrasonic sensor, RGB Camera, and NIR Camera along with a deep neural network accelerator for speeding up computation. We show that by adaptively choosing the appropriate sensor for the context, we can achieve up to 90% reduction in energy while maintaining comparable performance to a single sensor system.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115652867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"GRanDE: Graphical Representation and Design Space Exploration of Embedded Systems","authors":"Rajesh Kedia, Mahesh Balakrishnan, K. Paul","doi":"10.1109/DSD.2019.00012","DOIUrl":"https://doi.org/10.1109/DSD.2019.00012","url":null,"abstract":"Tasks executing computer vision and machine learning algorithms are becoming popular on embedded platforms. A key characteristic of such tasks is the presence of modes providing different levels of application performance in terms of metrics like accuracy. The system designer has the flexibility to select an appropriate mode for executing such tasks. Secondly, the designer also has the traditional flexibility of choosing suitable components to build the execution platform. Thirdly, the system performance might vary with various external factors (known as context), and during the initial stages of system design, the designer might have the flexibility to support only a subset of the possible contexts. This three-fold flexibility in the hands of the designer has not been explored simultaneously in prior works and raises the complexity of designing embedded systems many-fold. In this paper, we address the design of such systems through a novel framework named GRanDE (Graphical Representation and Design Space Exploration). GRanDE consists of a comprehensive graphical representation to capture the three aspects of the design space discussed earlier. Further, we transform this representation into Constraint Logic Programming (CLP) constructs, which could be used to interactively explore and prune the design space. We demonstrate the applicability of the proposed framework on an embedded system named MAVI having ~1.3 million design points. The generated CLP program could prune up to 99.74% of the design space of MAVI.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116994490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"System Design of an Open-Source Cloud-Based Framework for Internet of Drones Application","authors":"Golizheh Mehrooz, E. Ebeid, Peter Schneider-Kamp","doi":"10.1109/DSD.2019.00087","DOIUrl":"https://doi.org/10.1109/DSD.2019.00087","url":null,"abstract":"Unmanned Aerial Vehicles (UAV) are increasingly gaining interest in Internet of Drones (IoD) applications for automatizing the labor-intensive tasks. They are used in various areas such as infrastructure inspection. However, UAVs have limited energy resources and computational processing capabilities, which prevents them from running applications onboard and accessing the internet for gaining knowledge about their mission. In order to address these challenges imposed by limited resource on the drone, we propose a new cloud system infrastructure for building open-source IoD applications. We have designed a client-server architecture which hosts the drone as a client and the cloud as a scalable server. For validating the developed IoD application, an open-source drone simulator and flight controller are adopted to perform the tests. The overall architecture of a drone-cloud framework is presented along with a use case to show the applicability of the proposed framework.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114983149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Mert, Hasan Azgin, Ercan Kalali, Ilker Hamzaoglu
{"title":"Novel Approximate Absolute Difference Hardware","authors":"A. Mert, Hasan Azgin, Ercan Kalali, Ilker Hamzaoglu","doi":"10.1109/DSD.2019.00036","DOIUrl":"https://doi.org/10.1109/DSD.2019.00036","url":null,"abstract":"Approximate hardware designs have higher performance, smaller area or lower power consumption than exact hardware designs at the expense of lower accuracy. Absolute difference (AD) operation is heavily used in many applications such as motion estimation (ME) for video compression, ME for frame rate conversion, stereo matching for depth estimation. Since most of the applications using AD operation are error tolerant by their nature, approximate hardware designs can be used in these applications. In this paper, novel approximate AD hardware designs are proposed. The proposed approximate AD hardware implementations have higher performance, smaller area and lower power consumption than exact AD hardware implementations at the expense of lower accuracy. They also have less error, smaller area and lower power consumption than the approximate AD hardware implementations which use approximate adders proposed in the literature.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122824250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Javier E. Soto, Thomas Krohmer, Cecilia Hernández, M. Figueroa
{"title":"Hardware Acceleration of k-Mer Clustering using Locality-Sensitive Hashing","authors":"Javier E. Soto, Thomas Krohmer, Cecilia Hernández, M. Figueroa","doi":"10.1109/DSD.2019.00105","DOIUrl":"https://doi.org/10.1109/DSD.2019.00105","url":null,"abstract":"Clustering is an essential operation in many data analysis applications. In particular, bioinformatics and genome analysis use clustering to group similar components in sequence data, in order to find important patterns such as DNA motifs. In this paper, we present an algorithm that clusters DNA data using locality-sensitive hashing with MinHash to group similar subsequences in large Chip-seq datasets. Tested on a standard mESC dataset, the algorithm builds clusters that contain subsequences with high-score matches to known DNA motifs. We also describe the architecture and implementation of a hardware accelerator on a Xilinx Kintex-7 XC7K325T FPGA, that exploits the parallelism of the algorithm to cluster data with a throughput of one k-mer per clock cycle at 350MHz. The accelerator achieves a speedup of 91 compared to a parallel software implementation of the algorithm on a 24-core server.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"8 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124463399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}