{"title":"MARM-GA: Mapping Applications to Reconfigurable Mesh using Genetic Algorithm","authors":"P. Kullu, S. Tosun","doi":"10.1109/DSD.2019.00013","DOIUrl":null,"url":null,"abstract":"Rapidly decreasing size of the CMOS transistors allowed us to place more components on a single chip than ever before. In order to meet the performance demands of these dense designs, designers introduced an efficient communication paradigm, Network-on-Chip (NoC), instead of traditional wiring-based methods. Although mesh topology is most commonly used topology for NoC design, it has several problems such as network congestion and energy consumption. Reconfigurable mesh topology is a good alternative to traditional mesh since it gives more mapping and routing options for reducing network congestion. However, design automation tools still lack efficient mapping and routing algorithms for reconfigurable meshes. In this study, we propose a genetic algorithm (GA) based method that simultaneously maps the application nodes on 2D reconfigurable mesh structure and determines the routing paths between communicating pairs with the objective of energy minimization. We have applied our method on four benchmarks and compared our results against two heuristic strategies. Simulation results show the superiority of our proposed method over the existing ones in terms of energy consumption.","PeriodicalId":217233,"journal":{"name":"2019 22nd Euromicro Conference on Digital System Design (DSD)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 22nd Euromicro Conference on Digital System Design (DSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DSD.2019.00013","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Rapidly decreasing size of the CMOS transistors allowed us to place more components on a single chip than ever before. In order to meet the performance demands of these dense designs, designers introduced an efficient communication paradigm, Network-on-Chip (NoC), instead of traditional wiring-based methods. Although mesh topology is most commonly used topology for NoC design, it has several problems such as network congestion and energy consumption. Reconfigurable mesh topology is a good alternative to traditional mesh since it gives more mapping and routing options for reducing network congestion. However, design automation tools still lack efficient mapping and routing algorithms for reconfigurable meshes. In this study, we propose a genetic algorithm (GA) based method that simultaneously maps the application nodes on 2D reconfigurable mesh structure and determines the routing paths between communicating pairs with the objective of energy minimization. We have applied our method on four benchmarks and compared our results against two heuristic strategies. Simulation results show the superiority of our proposed method over the existing ones in terms of energy consumption.