2023 IEEE European Test Symposium (ETS)最新文献_第3页

Error Resilient Transformers: A Novel Soft Error Vulnerability Guided Approach to Error Checking and Suppression 错误弹性变压器:一种新的软错误漏洞导向的错误检测与抑制方法

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174239

Kwondo Ma, C. Amarnath, A. Chatterjee

{"title":"Error Resilient Transformers: A Novel Soft Error Vulnerability Guided Approach to Error Checking and Suppression","authors":"Kwondo Ma, C. Amarnath, A. Chatterjee","doi":"10.1109/ETS56758.2023.10174239","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174239","url":null,"abstract":"Transformer networks have achieved remarkable success in Natural Language Processing (NLP) and Computer Vision applications. However, the underlying large volumes of Transformer computations demand high reliability and resilience to soft errors in processor hardware. The objective of this research is to develop efficient techniques for design of error resilient Transformer architectures. To enable this, we first perform a soft error vulnerability analysis of every fully connected layers in Transformer computations. Based on this study, error detection and suppression modules are selectively introduced into datapaths to restore Transformer performance under anticipated error rate conditions. Memory access errors and neuron output errors are detected using checksums of linear Transformer computations. Correction consists of determining output neurons with out-of-range values and suppressing the same to zero. For a Transformer with nominal BLEU score of 52.7, such vulnerability guided selective error suppression can recover language translation performance from a BLEU score of 0 to 50.774 with as much as 0.001 probability of activation error, incurring negligible memory and computation overheads.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"23 Vol. 23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127670763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Learn to Tune: Robust Performance Tuning in Post-Silicon Validation 学会调优:后硅验证中的稳健性能调优

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174123

P. Domanski, D. Pflüger, Raphael Latty

引用次数: 0

Understanding Permanent Hardware Failures in Deep Learning Training Accelerator Systems 理解深度学习训练加速器系统中的永久性硬件故障

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10173972

Yi He, Yanjing Li

{"title":"Understanding Permanent Hardware Failures in Deep Learning Training Accelerator Systems","authors":"Yi He, Yanjing Li","doi":"10.1109/ETS56758.2023.10173972","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173972","url":null,"abstract":"Hardware failures pose critical threats to deep neural network (DNN) training workloads, and the urgency of tackling this challenge (known as the Silent Data Corruption challenge in a broader context) has been raised widely by the industry. Based on industry reports, a large number of the failures observed in real systems are permanent hardware failures in logic. However, there is a very limited understanding of the effects that these failures can impose on DNN training workloads. In this paper, we present the first resilience study on this subject, focusing on deep learning (DL) training accelerator systems. We developed a fault injection framework to accurately simulate the effects of permanent faults, and conducted 100K fault injection experiments. Our results provide the fundamental understanding on how logic permanent hardware failures affect training workloads and eventually generate unexpected training outcomes. Based on this new knowledge, we developed efficient software-based detection and recovery techniques to mitigate logic permanent hardware failures that are likely to generate unexpected outcomes. Evaluation on Google Cloud TPUs shows that our techniques are effective and practical: they require 15−25 lines of code change, and introduce 0.004%−0.025% performance/energy overhead for various representative neural network models.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117249086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On Using Cell-Aware Methodology for SRAM Bit Cell Testing 基于单元感知的SRAM位单元测试方法研究

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174118

X. Xhafa, A. Ladhar, E. Faehn, L. Anghel, G. D. Pendina, P. Girard, A. Virazel

引用次数: 0

BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell 内置自测试软错误强化扫描单元

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174154

S. Holst, Ruijun Ma, X. Wen, Aibin Yan, Hui Xu

引用次数: 0

Dependability of Future Edge-AI Processors: Pandora’s Box 未来边缘ai处理器的可靠性:潘多拉的盒子

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174180

M. Gomony, A. Gebregiorgis, M. Fieback, M. Geilen, S. Stuijk, Jan Richter-Brockmann, R. Bishnoi, Sven Argo, Lara Arche Andradas, T. Güneysu, M. Taouil, H. Corporaal, S. Hamdioui

引用次数: 0

Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips 芯片上多功率域系统的IJTAG网络综合

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174127

P. Habiby, N. Lylina, Chih-Hao Wang, H. Wunderlich, S. Huhn, R. Drechsler

{"title":"Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips","authors":"P. Habiby, N. Lylina, Chih-Hao Wang, H. Wunderlich, S. Huhn, R. Drechsler","doi":"10.1109/ETS56758.2023.10174127","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174127","url":null,"abstract":"The high-volume manufacturing test ensures the production of defect-free devices, which is of utmost importance when dealing with safety-critical systems. Such a high-quality test requires a deliberately designed scan network to provide a time and cost-effective access to many on-chip components, as included in state-of-the-art chip designs. The IEEE 1687 Std. (IJTAG) has been introduced to tackle this challenge by adding programmable components that enables the design of reconfigurable scan networks. Although these networks reduce the test time by shortening the scan chains’ lengths, the reconfiguration process itself incurs an additional time overhead. This paper proposes a heuristic method for designing customized multi-power domain reconfigurable scan networks with a minimized overall reconfiguration time. More precisely, the proposed method exploits a-priori given non-functional properties of the system, such as the power characteristics and the instruments’ access requirements. For the first time, these non-functional properties are considered to synthesize a well-adjusted and highly efficient multi-power domain network. The experimental results show a considerable improvement over the reported benchmark networks.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121833958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Secrets Leaking Through Quicksand: Covert Channels in Approximate Computing 通过流沙泄漏的秘密:近似计算中的隐蔽通道

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174181

Lorenzo Masciullo, R. Passerone, F. Regazzoni, I. Polian

引用次数: 0

Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods 使用形式化方法增加逻辑锁定机制的sat弹性

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10173975

M. Merten, S. Huhn, R. Drechsler

{"title":"Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods","authors":"M. Merten, S. Huhn, R. Drechsler","doi":"10.1109/ETS56758.2023.10173975","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173975","url":null,"abstract":"Today, Integrated Circuits (ICs) manufactoring is distributed over various foundries, resulting in untrustworthy supply chains. Therefore, significant concerns about malicious intentions like intellectual property piracy of the fabricated ICs exist. Logic Locking (LL) is one well-known protection technique to improve the security of ICs. However, there are approaches to unlocking the circuit, like the SAT-based attack. Significant research has been done on thwarting the SAT-based attack by providing SAT-resilient LL. Nevertheless, these SAT-resilient LL approaches have an inherent structural footprint, yielding a high vulnerability to structural attacks. Recently, Polymorphic Logic Gates (PLGs) have been utilized to implement logic obfuscation by replacing gates. Reconfigurable Field Effect Transistors (RFETs) are a new emerging technology for implementing such PLGs due to their inherent camouflaging properties. This work proposes a novel technique for increasing SAT-resilience while introducing no structural weakness using those PLGs. In particular, based on the concept of an SAT-based attack, a procedure for determining the most SAT-resilient placement of LL-cells is developed. The experimental evaluation proves that the proposed hardening of the placement increases the SAT-resilience compared to a random placement while providing inherent camouflaging of RFET-cells.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"64 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131960854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Attacking Memristor-Mapped Graph Neural Network by Inducing Slow-to-Write Errors 通过诱导慢写错误攻击忆阻器映射图神经网络

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174062

Ching-Yuan Chen, Biresh Kumar Joardar, J. Doppa, P. Pande, K. Chakrabarty

引用次数: 0