2023 IEEE European Test Symposium (ETS)最新文献_第7页

Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture 晶圆厂8T sram基IMC架构的胞内阻开缺陷分析

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174107

L. Ammoura, M. Flottes, P. Girard, J. Noel, A. Virazel

引用次数: 0

FINaL: Driving High-Level Fault Injection Campaigns with Natural Language 最后:用自然语言驱动高级故障注入活动

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174150

Khaled Galal Abdelwahab Abdelaziz, Ralph Görgen, Goerschwin Fey

引用次数: 0

Criticality Analysis of Ring Oscillators in FPGA Bitstreams * FPGA位流中环形振荡器的临界分析*

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10173861

Jayeeta Chaudhuri, K. Chakrabarty

{"title":"Criticality Analysis of Ring Oscillators in FPGA Bitstreams *","authors":"Jayeeta Chaudhuri, K. Chakrabarty","doi":"10.1109/ETS56758.2023.10173861","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173861","url":null,"abstract":"The popularity of cloud computing has led to increasing demand for efficient and scalable hardware. Multitenant FPGAs are becoming popular because of their ability to provide high performance and flexibility, yet being cost-effective. While multiple tenants have the ability to configure the same FPGA with customized modules, several security vulnerabilities can be exploited by adversaries. Attackers can use an FPGA to perform malicious actions, such as injecting malicious bitstreams and launching denial-of-service attacks. We propose a two-tier machine learning framework that first detects malicious features from an FPGA bitstream and then performs criticality analysis to evaluate the severity of potentially malicious ring oscillators (ROs) configured by that bitstream. The latter step is crucial as it ensures the security of FPGAs from voltage and power-based attacks and also reduces the risk of inappropriately blocking benign RO-based circuits from FPGA configuration. The proposed framework is evaluated using a diverse set of real-world bitstreams. We achieve an accuracy of 100% in detecting malicious bitstreams and an accuracy of 96.55% in detecting malicious bitstreams that are critical.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123894429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Side-Channel Attack on a Hardware Implementation of CRYSTALS-Kyber crystal - kyber硬件实现中的侧信道攻击

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174000

Yan Ji, Ruize Wang, Kalle Ngo, E. Dubrova, Linus Backlund

引用次数: 9

Density-oriented diagnostic data compression strategy for characterization of embedded memories in Automotive Systems-on-Chip 面向密度的汽车片上系统嵌入式存储器表征诊断数据压缩策略

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174126

Giorgio Insinga, M. Battilana, M. Coppetta, N. Mautone, G. Carnevale, M. Giltrelli, P. Scaramuzza, R. Ullmann

{"title":"Density-oriented diagnostic data compression strategy for characterization of embedded memories in Automotive Systems-on-Chip","authors":"Giorgio Insinga, M. Battilana, M. Coppetta, N. Mautone, G. Carnevale, M. Giltrelli, P. Scaramuzza, R. Ullmann","doi":"10.1109/ETS56758.2023.10174126","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174126","url":null,"abstract":"Embedded System-on-Chip (SoC) memory requirements in the Automotive industry are constantly growing. For this reason, memories occupy a significant part of Automotive SoC’s die area, increasing the defect probability inside the embedded storage. Automotive SoC manufacturers need to deeply test their embedded memories as they are one of the significant contributors to the yield of their devices. The test effort increases for the characterization of new technologies and new families of devices that need to be characterized by the manufacturers. These tests generate a massive quantity of diagnostic information that is incredibly valuable for designers and technology experts. This diagnostic information can be analyzed to identify and correct possible weaknesses and misbehavior. The easiest way to collect memory diagnostic information consists of failure bitmaps in which each fault is saved as coordinates. This method is the simplest solution to implement. However, logging the coordinates of every fault may generate an unmanageable quantity of data. This problem is exacerbated when there is an on-chip limitation on the amount of data that can be saved or transmitted to the external world.This paper presents an optimized on-chip compression algorithm that allows to reduce the required on-chip memory to store diagnostic information during embedded memory testing. This solution allows the reconstruction of a failure bitmap, generating a topological representation of the density of the failings bits in the embedded on-chip memory. The proposed approach effectively reduces the used storage to a fraction with respect to the one used by the original failing bitmap. The algorithm uses a coordinates-based approach, in which the memory is logically divided into equally divided sectors. The small time overhead introduced by the algorithm is compensated by the ability to achieve optimal space utilization.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127118761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications 用于硅自旋量子比特单电子晶体管室温筛选的晶体管指标研究

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10173954

Francesco Lorenzelli, A. Elsayed, C. Godfrin, A. Grill, S. Kubicek, Ruoyu Li, M. Stucchi, D. Wan, K. D. Greve, E. Marinissen, G. Gielen

{"title":"Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications","authors":"Francesco Lorenzelli, A. Elsayed, C. Godfrin, A. Grill, S. Kubicek, Ruoyu Li, M. Stucchi, D. Wan, K. D. Greve, E. Marinissen, G. Gielen","doi":"10.1109/ETS56758.2023.10173954","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173954","url":null,"abstract":"Quantum computers aim at solving computationally hard tasks exponentially faster than classical computers. Among the different platforms that are candidate for the realization of a large-scale fault-tolerant quantum computer, Si spin qubits are one of the most promising, due to their manufacturability and long coherence times. Spin qubits operate in a 3He/4He dilution refrigerator, featuring extremely low operating temperatures (tens of millikelvin) as well as long cool-down times. Testing at cryogenic temperature is extremely expensive, not only due to the required equipment and the long cool-down time, but also due to the limited number of packaged devices that can be tested in a single cool-down cycle. Our research aims at defining a parametric test routine for high-volume room-temperature screening of MOS Si spin qubit arrays, to select good candidates for cryogenic temperature testing. In this paper we measure Single Electron Transistors (SETs), that represent the overall quality of the array, and report experimental results to investigate which transistor metrics are more relevant for the device screening, comparing room-temperature data at 295K to 4K and 40mK data.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133402575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS EUROPULS:基于相变材料增强硅光子的神经形态节能安全加速器

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-04 DOI: 10.1109/ETS56758.2023.10173974

F. Pavanello, Cédric Marchand, I. O’Connor, R. Orobtchouk, F. Mandorlo, X. Letartre, S. Cueff, E. Vatajelu, G. D. Natale, B. Cluzel, A. Coillet, B. Charbonnier, P. Noé, Frantisek Kavan, M. Zoldak, Michal Szaj, P. Bienstman, T. Vaerenbergh, U. Rührmair, Paulo F. Flores, L. G. Silva, R. Chaves, Luis Miguel Silveira, M. Ceccato, D. Gizopoulos, G. Papadimitriou, Vasileios Karakostas, Axel Brando, F. Cazorla, Ramon Canal, P. Closas, Adria Gusi-Amigo, P. Crovetti, Alessio Carpegna, Tzamn Melendez Carmona, S. Carlo, A. Savino

{"title":"EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS","authors":"F. Pavanello, Cédric Marchand, I. O’Connor, R. Orobtchouk, F. Mandorlo, X. Letartre, S. Cueff, E. Vatajelu, G. D. Natale, B. Cluzel, A. Coillet, B. Charbonnier, P. Noé, Frantisek Kavan, M. Zoldak, Michal Szaj, P. Bienstman, T. Vaerenbergh, U. Rührmair, Paulo F. Flores, L. G. Silva, R. Chaves, Luis Miguel Silveira, M. Ceccato, D. Gizopoulos, G. Papadimitriou, Vasileios Karakostas, Axel Brando, F. Cazorla, Ramon Canal, P. Closas, Adria Gusi-Amigo, P. Crovetti, Alessio Carpegna, Tzamn Melendez Carmona, S. Carlo, A. Savino","doi":"10.1109/ETS56758.2023.10173974","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173974","url":null,"abstract":"This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. Our approach aims to develop an augmented silicon photonics platform, an FPGA-powered RISC-V-connected computing platform, and a complete simulation platform to demonstrate the neuromorphic accelerator capabilities. In particular, their main advantages and limitations will be addressed concerning the underpinning technology for each platform. Then, we will discuss three targeted use cases for edge-computing applications: Global National Satellite System (GNSS) anti-jamming, autonomous driving, and anomaly detection in edge devices. Finally, we will address the reliability and security aspects of the stand-alone accelerator implementation and the project use cases.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126741012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective 未来基于RISC-V的云基础设施的验证、验证和测试(VVT): Vitamin-V Horizon Europe项目视角

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-03 DOI: 10.1109/ETS56758.2023.10174216

Marti Alonso, David Andreu, R. Canal, S. Carlo, C. Chenet, Juanjo Costa, Andreu Girones, D. Gizopoulos, Vasileios Karakostas, Beatriz Otero, G. Papadimitriou, Eva Rodríguez, A. Savino

{"title":"Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective","authors":"Marti Alonso, David Andreu, R. Canal, S. Carlo, C. Chenet, Juanjo Costa, Andreu Girones, D. Gizopoulos, Vasileios Karakostas, Beatriz Otero, G. Papadimitriou, Eva Rodríguez, A. Savino","doi":"10.1109/ETS56758.2023.10174216","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174216","url":null,"abstract":"Vitamin-V is a project funded under the Horizon Europe program for the period 2023-2025. The project aims to create a complete open-source software stack for RISC-V that can be used for cloud services. This software stack is intended to have the same level of performance as the x86 architecture, which is currently dominant in the cloud computing industry. In addition, the project aims to create a powerful virtual execution environment that can be used for software development, validation, verification, and testing. The virtual environment will consider the relevant RISC-V ISA extensions required for cloud deployment. Commercial cloud systems use hardware features currently unavailable in RISC-V virtual environments, including virtualization, cryptography, and vectorization. To address this, Vitamin-V will support these features in three virtual environments: QEMU, gem5, and cloud-FPGA prototype platforms. The project will focus on providing support for EPI-based RISC-V designs for both the main CPUs and cloud-important accelerators, such as memory compression. The project will add the compiler (LLVM-based) and toolchain support for the ISA extensions. Moreover, Vitamin-V will develop novel approaches for validating, verifying, and testing software trustworthiness. This paper focuses on the plans and visions that the Vitamin-V project has to support validation, verification, and testing for cloud applications, particularly emphasizing the hardware support that will be provided.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130693346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs’ Reliability Assessment 深度神经网络可靠性评估的脆弱性取值范围及影响因素

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-03-13 DOI: 10.1109/ETS56758.2023.10174133

Mohammad Hasan Ahmadilivani, Mahdi Taheri, J. Raik, M. Daneshtalab, M. Jenihhin

{"title":"DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs’ Reliability Assessment","authors":"Mohammad Hasan Ahmadilivani, Mahdi Taheri, J. Raik, M. Daneshtalab, M. Jenihhin","doi":"10.1109/ETS56758.2023.10174133","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174133","url":null,"abstract":"Deep Neural Networks (DNNs) and their accelerators are being deployed ever more frequently in safety-critical applications leading to increasing reliability concerns. A traditional and accurate method for assessing DNNs’ reliability has been resorting to fault injection, which, however, suffers from prohibitive time complexity. While analytical and hybrid fault injection-/analytical-based methods have been proposed, they are either inaccurate or specific to particular accelerator architectures.In this work, we propose a novel accurate, fine-grain, metric-oriented, and accelerator-agnostic method called DeepVigor that provides vulnerability value ranges for DNN neurons’ outputs. An outcome of DeepVigor is an analytical model representing vulnerable and non-vulnerable ranges for each neuron that can be exploited to develop different techniques for improving DNNs’ reliability. Moreover, DeepVigor provides reliability assessment metrics based on vulnerability factors for bits, neurons, and layers using the vulnerability ranges.The proposed method is not only faster than fault injection but also provides extensive and accurate information about the reliability of DNNs, independent from the accelerator. The experimental evaluations in the paper indicate that the proposed vulnerability ranges are 99.9% to 100% accurate even when evaluated on previously unseen test data. Also, it is shown that the obtained vulnerability factors represent the criticality of bits, neurons, and layers proficiently. DeepVigor is implemented in the PyTorch framework and validated on complex DNN benchmarks.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121406161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Micro-Architectural features as soft-error markers in embedded safety-critical systems: preliminary study 微架构特征作为嵌入式安全关键系统中的软错误标记:初步研究

2023 IEEE European Test Symposium (ETS) Pub Date : 2022-11-23 DOI: 10.1109/ETS56758.2023.10174219

Deniz Kasap, Alessio Carpegna, A. Savino, S. Carlo

{"title":"Micro-Architectural features as soft-error markers in embedded safety-critical systems: preliminary study","authors":"Deniz Kasap, Alessio Carpegna, A. Savino, S. Carlo","doi":"10.1109/ETS56758.2023.10174219","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174219","url":null,"abstract":"Radiation-induced soft errors are one of the most challenging issues in Safety Critical Real-Time Embedded System (SACRES) reliability, usually handled using different flavors of Double Modular Redundancy (DMR) techniques. This solution is becoming unaffordable due to the complexity of modern micro-processors in all domains. This paper addresses the promising field of using Artificial Intelligence (AI) based hardware detectors for soft errors. To create such cores and make them general enough to work with different software applications, micro-architectural attributes are a fascinating option as candidate fault detection features. Several processors already track these features through dedicated Performance Monitoring Unit (PMU). However, there is an open question to understand to what extent they are enough to detect faulty executions. Exploiting the capability of gem5 to simulate real computing systems, perform fault injection experiments, and profile micro-architectural attributes (i.e., gem5 Stats), this paper presents the results of a comprehensive analysis regarding the potential attributes to detect soft errors and the associated models that can be trained with these features.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116197133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0