2023 IEEE European Test Symposium (ETS)最新文献_第6页

Semi-Supervised Deep Learning for Microcontroller Performance Screening 微控制器性能筛选的半监督深度学习

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174083

N. Bellarmino, R. Cantoro, M. Huch, T. Kilian, Ulf Schlichtmann, Giovanni Squillero

{"title":"Semi-Supervised Deep Learning for Microcontroller Performance Screening","authors":"N. Bellarmino, R. Cantoro, M. Huch, T. Kilian, Ulf Schlichtmann, Giovanni Squillero","doi":"10.1109/ETS56758.2023.10174083","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174083","url":null,"abstract":"In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of Fmax (the maximum operating frequency). Data extracted from on-chip ring oscillators (ROs) can model the Fmax of integrated circuits using machine learning models. Those models are suitable for the performance screening process. Acquiring data from the ROs is a fast process that leads to many unlabeled data. Contrarily, the labeling phase (i.e., acquiring Fmax) is a time-consuming and costly task, that leads to a small set of labeled data. This paper presents deep-learning-based methodologies to cope with the low number of labeled data in microcontroller performance screening. We propose a method that takes advantage of the high number of unlabeled samples in a semi-supervised learning fashion. We derive deep feature extractor models that project data into higher dimensional spaces and use the data feature embedding to face the performance prediction problem with simple linear regression. Experiments showed that the proposed models outperformed state-of-the-art methodologies in terms of prediction error and permitted us to use a significantly smaller number of devices to be characterized, thus reducing the time needed to build ML models by a factor of six with respect to baseline approaches.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"14 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114081138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Physical-aware Interconnect Testing and Repairing of Chiplets 小芯片的物理感知互连测试与修复

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174179

C. Cui, Tuanhui Xu, Haitao Fu, Junlin Huang

引用次数: 0

High Throughput and Energy Efficient SHA-2 ASIC Design for Continuous Integrity Checking Applications 用于持续完整性检查应用的高通量和节能SHA-2 ASIC设计

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174095

Asimina Koutra, V. Tenentes

引用次数: 0

Online Fault-Tolerance for Memristive Neuromorphic Fabric Based on Local Approximation 基于局部逼近的记忆神经形态网络在线容错

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174237

Soyed Tuhin Ahmed, R. Rakhmatullin, M. Tahoori

引用次数: 1

Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs rram中所有互连和接触缺陷的数据背景测试开发

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174106

Hanzhi Xun, M. Fieback, S. Yuan, Ziwei Zhang, M. Taouil, S. Hamdioui

{"title":"Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs","authors":"Hanzhi Xun, M. Fieback, S. Yuan, Ziwei Zhang, M. Taouil, S. Hamdioui","doi":"10.1109/ETS56758.2023.10174106","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174106","url":null,"abstract":"Resistive Random Access Memory (RRAM) is a potential technology to replace conventional memories by providing low power consumption and high-density storage. As various manufacturing vendors make significant efforts to push it to high-volume production and commercialization, high-quality and efficient test solutions are of great importance. This paper analyzes interconnect and contact defects in RRAMs, while considering the impact of the memory Data Background (DB), and proposes test solutions. The complete interconnect and contact defect space in a layout-independent RRAM design is defined. Exhaustive defect injection and circuit simulation are performed in a systematic manner to derive appropriate fault models, not only for single-cell and two-cell coupling faults, but also for multi-cell coupling faults where the DBs are important. The results show the existence of unique 3-cell and 4-cell coupling faults due to e.g., the sneak path in the array induced by defects. These unique faults cannot be detected with traditional RRAM test solutions. Therefore, the paper introduces a test generation method that takes into account the DB, which is able to efficiently detect all these faults; hence, further improving the fault/defect coverage in RRAMs.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125330838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSI 用于纳米级超大规模集成电路硅生命周期管理的片上电迁移传感器

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10173993

M. Mayahinia, M. Tahoori, Grigor Tshagharyan, Gurgen Harutunyan, Y. Zorian

{"title":"On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSI","authors":"M. Mayahinia, M. Tahoori, Grigor Tshagharyan, Gurgen Harutunyan, Y. Zorian","doi":"10.1109/ETS56758.2023.10173993","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173993","url":null,"abstract":"The advanced CMOS technology with smaller feature sizes has greatly improved the performance, energy, and area efficiency of the VLSI systems. Alongside the transistor feature size, back-end-of-the-line (BEoL) interconnects are also shrinking which makes them susceptible to electromigration (EM). Current density and temperature have decisive impacts on the EM profile of the BEoL interconnects, which themselves are highly affected by the running workload. Hence, the actual degradation and the remaining lifetime of a VLSI system are impacted by its usage scenarios. Therefore, in-field monitoring of the chip usage can predict failures before they happen and cause catastrophic failures, and in addition, provide an accurate estimate of the remaining useful lifetime to schedule preventive maintenance. In this work, we propose a simple yet effective on-chip EM sensor that can be embedded as a part of chip silicon lifecycle management (SLM) infrastructure. Further, we show how our proposed EM sensor can be effectively leveraged as a general sensor for the estimation of the remaining useful lifetime of the chip. The simulation results for the 5nm realistic SRAM design show that the power overhead of the proposed sensor is only 0.00365% of the SRAM module with a negligible area overhead.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125430356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse Engineering BitFREE: FPGA比特流格式逆向工程的显著加速和安全应用

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174155

Zhang Tao, M. Tehranipoor, Farimah Farahmandi

{"title":"BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse Engineering","authors":"Zhang Tao, M. Tehranipoor, Farimah Farahmandi","doi":"10.1109/ETS56758.2023.10174155","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174155","url":null,"abstract":"FPGAs have been widely deployed in critical applications ranging from consumer electronics to spacecraft while the mainstream vendors refuse to disclose the details of their configuration bitstream format for security considerations but obstruct benign applications at the same time. Despite several bitstream reverse engineering solutions being proposed to reconstruct the bitstream formats, the state-of-the-art techniques typically require at least days to partially retrieve the architecture-specific bitstream format for a single (small) FPGA model. In this paper, we propose our BitFREE methodology which targets the most market-dominating Xilinx devices to reverse engineer the majority of bitstream formats of all models in different FPGA families at the time in the order of minutes by utilizing the correlation between FPGA architecture and the configuration memory map to decompose the configuration frames into more fine-grained segments for intelligent parallel analysis instead of directly analyzing entire bitstreams serially like other works. We demonstrate the high accuracy of BitFREE by recovering the information precisely from bitstreams of covered FPGA models. Also, we introduce two security applications of BitFREE, i.e., routing-level bitstream tampering and malicious ring oscillator circuitry detection, to shed light on the broad usage of bitstream reverse engineering in the hardware security domain.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123023662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs 图像测试库用于运行cnn的gpu的功能单元在线自测

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174176

A. Ruospo, G. Gavarini, A. Porsia, M. Reorda, Ernesto Sánchez, R. Mariani, J. Aribido, J. Athavale

{"title":"Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs","authors":"A. Ruospo, G. Gavarini, A. Porsia, M. Reorda, Ernesto Sánchez, R. Mariani, J. Aribido, J. Athavale","doi":"10.1109/ETS56758.2023.10174176","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174176","url":null,"abstract":"The widespread use of artificial intelligence (AI)-based systems has raised several concerns about their deployment in safety-critical systems. Industry standards, such as ISO26262 for automotive, require detecting hardware faults during the mission of the device. Similarly, new standards are being released concerning the functional safety of AI systems (e.g., ISO/IEC CD TR 5469). Hardware solutions have been proposed for the infield testing of the hardware executing AI applications; however, when used in applications such as Convolutional Neural Networks (CNNs) in image processing tasks, their usage may increase the hardware cost and affect the application performances. In this paper, for the very first time, a methodology to develop high-quality test images, to be interleaved with the normal inference process of the CNN application is proposed. An Image Test Library (ITL) is developed targeting the on-line test of GPU functional units. The proposed approach does not require changing the actual CNN (thus incurring in costly memory loading operations) since it is able to exploit the actual CNN structure. Experimental results show that a 6-image ITL is able to achieve about 95% of stuck-at test coverage on the floating-point multipliers in a GPU. The obtained ITL requires a very low test application time, as well as a very low memory space for storing the test images and the golden test responses.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121789799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

ETS 2022 Best Paper ETS 2022年最佳论文

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ets56758.2023.10174187

引用次数: 0

SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs SiCBit-PUF:用于可信soc的强缓存内位翻转PUF计算

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10173941

Athanasios Xynos, V. Tenentes, Y. Tsiatouhas

{"title":"SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs","authors":"Athanasios Xynos, V. Tenentes, Y. Tsiatouhas","doi":"10.1109/ETS56758.2023.10173941","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173941","url":null,"abstract":"Secure computing necessitates hardware root of trust (RoT) integrated in Systems-on-Chips (SoCs) for cryptographic keys generation, authentication and identification. In this paper, we observe that bitflips in SRAM cells that appear while accessing multiple cells from the same bitline, are not stochastic, as previously considered, but systematic. Based on this observation, a novel strong in-memory Physical Unclonable Function (PUF) computation is proposed for harvesting static entropy from SRAM arrays. The proposed design is compatible with existing in-SRAM computing architectures. To verify our PUF operation, we implement a 6T SRAM array model that performs in-memory computing using a 32 nm CMOS Technology, and, through SPICE simulation, we evaluate the proposed PUF performance. The proposed PUF operation achieves uniqueness and uniformity of 49.99%, and 49.74%, respectively, and reliability higher than 97.4% when the temperature is varied from 0°C to 100°C, and higher than 95.2% when the nominal voltage supply is varied by 10%. Furthermore, we explore the scaling of the number of Challenge Response Pairs (CRPs) of the proposed PUF, and we compare it against the state-of-the-art. Our PUF offers orders of magnitude higher number of CRPs, therefore it is suitable for integrated mechanisms that assure secure computing in SoCs.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129169428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0