2023 IEEE European Test Symposium (ETS)最新文献

Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants 联机可靠性评估设计:仲裁者PUF及其变体的可靠crp选择

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174198

Chaofang Ma, Jianan Mu, Jing Ye, Shuai Chen, Yuan Cao, Huawei Li, Xiaowei Li

{"title":"Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants","authors":"Chaofang Ma, Jianan Mu, Jing Ye, Shuai Chen, Yuan Cao, Huawei Li, Xiaowei Li","doi":"10.1109/ETS56758.2023.10174198","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174198","url":null,"abstract":"Physical Unclonable Function (PUF) is a hardware security primitive with broad application prospects. Variants of the arbiter PUF have been proposed to resist modeling attacks. However, their low reliability issue limits their applications. To solve the low reliability issue, this paper proposes an Online Reliability Evaluation (ORE) design for the arbiter PUF and its variants. Moreover, a corresponding machine learning method to select reliable Challenge Response Pairs (CRPs) for applications is proposed. Based on the ORE design, a small number of CRPs and their reliability levels are collected during the enrollment phase. Then they are trained to build reliability models for predicting the responses and reliability levels of other challenges. Since the ORE design does not change the security structures of the arbiter PUF and its variants, the resistance to modeling attacks of PUF designs equipped with it is maintained. Compared to the previous work that tests 100,000 times per CRP, our design is time-saving in the enrollment phase since each CRP is only tested three times for training reliability models. The proposed design is implemented under the 40nm process. Experimental results on real chips show that all the CRPs selected by our reliability models are indeed reliable for applications, verifying the effectiveness of our method.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121354810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Harvesting Wasted Clock Cycles for Efficient Online Testing 为有效的在线测试收集浪费的时钟周期

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10173955

Eslam Yassien, Yongjia Xu, Hui Jiang, Thach Nguyen, Jennifer Dworak, T. Manikas, Kundan Nepal

引用次数: 0

Global Tuning for System Performance Optimization of RF MIMO Radars 射频MIMO雷达系统性能优化的全局调谐

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174159

Ferhat Can Ataman, Muslum Emir Avci, Chethan Kumar Y. B., S. Ozev

引用次数: 0

Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing 自动生成功能应力诱导刺激的老化测试

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174232

N. I. Deligiannis, Tobias Faller, Chenghan Zhou, R. Cantoro, B. Becker, M. Reorda

{"title":"Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing","authors":"N. I. Deligiannis, Tobias Faller, Chenghan Zhou, R. Cantoro, B. Becker, M. Reorda","doi":"10.1109/ETS56758.2023.10174232","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174232","url":null,"abstract":"In the domain of high reliability applications, Burn-In testing (BI) is always present since it is one of the prime countermeasures against the infant mortality phenomenon. Traditional static BI testing proves to be inefficient for modern circuit designs. As the devices’ feature size scales down and their structural and architectural complexity increases, so does the complexity and cost of the BI test. Different BI methods are employed by the industry where stimuli are also applied to the devices under test (DUTs) in order to effectively stress and stimulate all nets of the design. One known industry practice resorts to Design for Testability (DfT) infrastructures (e.g., scan) and is based on the application of test vectors at low frequency to excite the DUT as much as possible with the goal of switching each net of the design at least once. In this paper we consider the case where the layout of the circuit is known and propose two novel methods able to automatically produce functional stimuli to switch pairs of neighboring nodes (i.e., nodes that are placed within a specified distance in the DUT) in short periods of time. This solution has been shown to be able to trigger some latent defects in a circuit better than other methods. As a case study, we target functional units within a RISC-V processor (RI5CY). We show that the functional stimuli generated by the exact method described in the paper are able to achieve optimal results (i.e., the maximum functional switching of neighboring pairs), thus maximizing the chance that their at-speed application can activate weak points in the circuit.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121389494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Spotlight: An Impairing Packet Transmission Attack Targeting Specific Node in NoC-based TCMP 聚焦:基于noc的tcp协议中针对特定节点的破坏性数据包传输攻击

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174197

Jiaoyan Yao, Ying Zhang, Yifeng Hua, Yuanxiang Li, Jizhong Yang, Xin Chen

{"title":"Spotlight: An Impairing Packet Transmission Attack Targeting Specific Node in NoC-based TCMP","authors":"Jiaoyan Yao, Ying Zhang, Yifeng Hua, Yuanxiang Li, Jizhong Yang, Xin Chen","doi":"10.1109/ETS56758.2023.10174197","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174197","url":null,"abstract":"As the communication infrastructure utilized by Tiled Chip Multicore Processors (TCMP), Network-on-Chip (NoC) has been subject to serious security vulnerabilities due to hardware Trojans (HTs) concealed in potentially insecure 3PIPs. To satisfy the need for secure NoCs, it is vital to model potential attacks and analyze their impacts on NoC performance. This paper proposes a novel and covert HT model called Spotlight targeting specific victim node in XY-routing NoC to optimize the attacking effect. By inserting Trojans into special nodes and modifying the arbiters of input ports within the switch allocator of router, packets flowing to the victim node are unfairly treated causing considerable latency. As a result, the HT effectively degrades the transmission of packets while having a subtle impact on other NoC performance. The proposed HT is inserted into Garnet 2.0 of Gem5 simulator for performance evaluation. Experimental results indicate that the Spotlight attack increased the average delay of target packets by 12.16 cycles. Compared to some DoS attacks, the proposed Trojan affected packet transmission with fewer packets, causing minimal fluctuates in NoC metrics such as average latency. And the area and power overheads are only 0.94% and 0.11%, respectively.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127757457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Automating Greybox System-Level Test Generation 自动化灰盒系统级测试生成

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10173985

Denis Schwachhofer, M. Betka, Steffen Becker, S. Wagner, M. Sauer, I. Polian

引用次数: 1

Understanding and Improving GPUs' Reliability Combining Beam Experiments with Fault Simulation 波束实验与故障仿真相结合对gpu可靠性的认识与改进

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174206

F. Santos, L. Carro, P. Rech

{"title":"Understanding and Improving GPUs' Reliability Combining Beam Experiments with Fault Simulation","authors":"F. Santos, L. Carro, P. Rech","doi":"10.1109/ETS56758.2023.10174206","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174206","url":null,"abstract":"Graphics Processing Units (GPUs) are being employed in High Performance Computing (HPC) and safety-critical applications, such as autonomous vehicles. This market shift led to significant improvements in the programming frameworks and performance evaluation tools and concerns about their reliability. GPU reliability evaluation is extremely challenging due to the parallel nature and high complexity of GPU architectures. We conducted the first cross-layer GPU reliability evaluation to unveil (and mitigate) GPU vulnerabilities. The proposed evaluation is achieved by comparing and combining extensive high-energy neutron beam experiments, massive fault simulation campaigns at both Register-Transfer Level (RTL) and software levels, and application profiling. Based on this extensive and detailed analysis, a novel accurate methodology to accurately estimate GPUs application FIT rate is proposed. Moreover, by employing the knowledge obtained from the cross-layer reliability evaluation, two novel hardening solutions for HPC and safety-critical applications are proposed: (1) Reduced Precision Duplication With Comparison (RP-DWC), which executes a redundant copy in a reduced precision. RP-DWC delivers excellent fault coverage, up to 86%, with minimal execution time and energy consumption overheads (13% and 24%, respectively). (2) Dedicated software solutions for hardening Convolutional Neural Networks (CNNs) that can correct up to 98% of the CNN errors.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129404934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Beyond Neural Networks, Exploring the Future of Computing Hardware 超越神经网络，探索计算硬件的未来

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ets56758.2023.10174029

引用次数: 0

Learning-Based Characterization Models for Quality Assurance of Emerging Memory Technologies 基于学习的表征模型用于新兴存储技术的质量保证

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174202

Xhesila Xhafa, P. Girard, A. Virazel

引用次数: 0

High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis 使用低成本信号生成和输出响应分析的高覆盖模拟IP块测试生成方法

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10173963

Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, G. Gielen

{"title":"High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis","authors":"Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, G. Gielen","doi":"10.1109/ETS56758.2023.10173963","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173963","url":null,"abstract":"Today, testing of AMS circuits needs to improve quality towards ppb test escape levels as well as decrease the test development time to reduce the IC lead time. A defect-oriented solution can improve quality by focusing on structural tests that can detect defects more efficiently than traditional functional tests, while test reuse can decrease test development time on ICs built with reusable IP blocks. A defect-oriented built-in self-test (BIST) approach integrates both solutions. This paper proposes a test development methodology for analog IP blocks based on such defect-oriented BIST framework. The methodology allows for achieving the target defect coverage at the lowest possible cost. Co-designing the IP with the DfT structures allows accounting for any non-idealities that the DfT may add to the IP. Test structures cost is limited by using low-cost signal generation and a new output response analyzer (ORA). The proposed methodology is demonstrated on two case studies. The results show that coverages higher than 90% are possible using a simple digital pulse signal and an ORA with only 4 bits of accuracy, while coverages higher than 95% are possible with 6 bits, offering a good trade-off between coverage and cost.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128393572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0