自动生成功能应力诱导刺激的老化测试

N. I. Deligiannis, Tobias Faller, Chenghan Zhou, R. Cantoro, B. Becker, M. Reorda
{"title":"自动生成功能应力诱导刺激的老化测试","authors":"N. I. Deligiannis, Tobias Faller, Chenghan Zhou, R. Cantoro, B. Becker, M. Reorda","doi":"10.1109/ETS56758.2023.10174232","DOIUrl":null,"url":null,"abstract":"In the domain of high reliability applications, Burn-In testing (BI) is always present since it is one of the prime countermeasures against the infant mortality phenomenon. Traditional static BI testing proves to be inefficient for modern circuit designs. As the devices’ feature size scales down and their structural and architectural complexity increases, so does the complexity and cost of the BI test. Different BI methods are employed by the industry where stimuli are also applied to the devices under test (DUTs) in order to effectively stress and stimulate all nets of the design. One known industry practice resorts to Design for Testability (DfT) infrastructures (e.g., scan) and is based on the application of test vectors at low frequency to excite the DUT as much as possible with the goal of switching each net of the design at least once. In this paper we consider the case where the layout of the circuit is known and propose two novel methods able to automatically produce functional stimuli to switch pairs of neighboring nodes (i.e., nodes that are placed within a specified distance in the DUT) in short periods of time. This solution has been shown to be able to trigger some latent defects in a circuit better than other methods. As a case study, we target functional units within a RISC-V processor (RI5CY). We show that the functional stimuli generated by the exact method described in the paper are able to achieve optimal results (i.e., the maximum functional switching of neighboring pairs), thus maximizing the chance that their at-speed application can activate weak points in the circuit.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing\",\"authors\":\"N. I. Deligiannis, Tobias Faller, Chenghan Zhou, R. Cantoro, B. Becker, M. Reorda\",\"doi\":\"10.1109/ETS56758.2023.10174232\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the domain of high reliability applications, Burn-In testing (BI) is always present since it is one of the prime countermeasures against the infant mortality phenomenon. Traditional static BI testing proves to be inefficient for modern circuit designs. As the devices’ feature size scales down and their structural and architectural complexity increases, so does the complexity and cost of the BI test. Different BI methods are employed by the industry where stimuli are also applied to the devices under test (DUTs) in order to effectively stress and stimulate all nets of the design. One known industry practice resorts to Design for Testability (DfT) infrastructures (e.g., scan) and is based on the application of test vectors at low frequency to excite the DUT as much as possible with the goal of switching each net of the design at least once. In this paper we consider the case where the layout of the circuit is known and propose two novel methods able to automatically produce functional stimuli to switch pairs of neighboring nodes (i.e., nodes that are placed within a specified distance in the DUT) in short periods of time. This solution has been shown to be able to trigger some latent defects in a circuit better than other methods. As a case study, we target functional units within a RISC-V processor (RI5CY). We show that the functional stimuli generated by the exact method described in the paper are able to achieve optimal results (i.e., the maximum functional switching of neighboring pairs), thus maximizing the chance that their at-speed application can activate weak points in the circuit.\",\"PeriodicalId\":211522,\"journal\":{\"name\":\"2023 IEEE European Test Symposium (ETS)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE European Test Symposium (ETS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ETS56758.2023.10174232\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE European Test Symposium (ETS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ETS56758.2023.10174232","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

在高可靠性应用领域,老化测试(BI)一直存在,因为它是防止婴儿死亡现象的主要对策之一。传统的静态BI测试在现代电路设计中被证明是低效的。随着设备的功能尺寸缩小,其结构和架构复杂性增加,BI测试的复杂性和成本也随之增加。工业采用了不同的BI方法,其中刺激也应用于被测设备(dut),以便有效地对设计的所有网络施加压力和刺激。一个已知的行业实践是采用可测试性设计(DfT)基础设施(例如,扫描),并基于低频测试向量的应用,以尽可能多地激发被测设备,目标是至少切换设计的每个网络一次。在本文中,我们考虑了电路布局已知的情况,并提出了两种新颖的方法,能够在短时间内自动产生功能刺激来切换相邻节点对(即,在DUT中放置在指定距离内的节点)。这种解决方案已被证明能够比其他方法更好地触发电路中的一些潜在缺陷。作为一个案例研究,我们的目标是RISC-V处理器(RI5CY)中的功能单元。我们表明,由本文中描述的精确方法产生的功能刺激能够达到最佳结果(即相邻对的最大功能切换),从而最大限度地提高了它们的高速应用可以激活电路中的弱点的机会。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing
In the domain of high reliability applications, Burn-In testing (BI) is always present since it is one of the prime countermeasures against the infant mortality phenomenon. Traditional static BI testing proves to be inefficient for modern circuit designs. As the devices’ feature size scales down and their structural and architectural complexity increases, so does the complexity and cost of the BI test. Different BI methods are employed by the industry where stimuli are also applied to the devices under test (DUTs) in order to effectively stress and stimulate all nets of the design. One known industry practice resorts to Design for Testability (DfT) infrastructures (e.g., scan) and is based on the application of test vectors at low frequency to excite the DUT as much as possible with the goal of switching each net of the design at least once. In this paper we consider the case where the layout of the circuit is known and propose two novel methods able to automatically produce functional stimuli to switch pairs of neighboring nodes (i.e., nodes that are placed within a specified distance in the DUT) in short periods of time. This solution has been shown to be able to trigger some latent defects in a circuit better than other methods. As a case study, we target functional units within a RISC-V processor (RI5CY). We show that the functional stimuli generated by the exact method described in the paper are able to achieve optimal results (i.e., the maximum functional switching of neighboring pairs), thus maximizing the chance that their at-speed application can activate weak points in the circuit.
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