2023 IEEE European Test Symposium (ETS)最新文献_第2页

On-Line Testing of Neuromorphic Hardware 神经形态硬件的在线测试

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174077

Theofilos Spyrou, H. Stratigopoulos

引用次数: 1

Power Side-Channel Attacks and Countermeasures on Computation-in-Memory Architectures and Technologies 内存中计算架构与技术的功率侧信道攻击与对策

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10173981

B. Sapui, Jonas Krautter, M. Mayahinia, A. Jafari, Dennis R. E. Gnad, Sergej Meschkov, M. Tahoori

{"title":"Power Side-Channel Attacks and Countermeasures on Computation-in-Memory Architectures and Technologies","authors":"B. Sapui, Jonas Krautter, M. Mayahinia, A. Jafari, Dennis R. E. Gnad, Sergej Meschkov, M. Tahoori","doi":"10.1109/ETS56758.2023.10173981","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173981","url":null,"abstract":"To overcome the bottleneck of the classical processor-centric architectures, Computation-in-Memory (CiM) is a promising paradigm where operations are performed directly in memory. Recent works propose the use of CiM to accelerate neural networks or hyperdimensional computing, but also for memory encryption solutions. As CiM facilitates the computation in the analog domain and the output is driven through current sensing, CiM could potentially be highly vulnerable to power side-channel attacks. In this work, we analyze the vulnerability for power side-channel attacks in various CiM implementations based on Static Random Access Memory (SRAM) and emerging nonvolatile memristive technologies. Our results show that a side-channel attacker can recover secret data used in an XOR operation with only a few hundred measurements, where CiM architectures based on emerging memristive technologies are more vulnerable than SRAM-based CiM. Therefore, we propose two different types of countermeasures based on hiding and masking, which are tailored to CiM architectures. The efficiency of our proposed countermeasures is shown by both attacks and leakage assessment methodologies using one million measurement traces.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128618543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of DNNs harDNNing:基于机器学习的深度神经网络容错评估和保护框架

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174178

Marcello Traiola, A. Kritikakou, O. Sentieys

{"title":"harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of DNNs","authors":"Marcello Traiola, A. Kritikakou, O. Sentieys","doi":"10.1109/ETS56758.2023.10174178","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174178","url":null,"abstract":"Deep Neural Networks (DNNs) show promising performance in several application domains, such as robotics, aerospace, smart healthcare, and autonomous driving. Nevertheless, DNN results may be incorrect, not only because of the network intrinsic inaccuracy, but also due to faults affecting the hardware. Indeed, hardware faults may impact the DNN inference process and lead to prediction failures. Therefore, ensuring the fault tolerance of DNN is crucial. However, common fault tolerance approaches are not cost-effective for DNNs protection, because of the prohibitive overheads due to the large size of DNNs and of the required memory for parameter storage. In this work, we propose a comprehensive framework to assess the fault tolerance of DNNs and cost-effectively protect them. As a first step, the proposed framework performs data-type-and-layer-based fault injection, driven by the DNN characteristics. As a second step, it uses classification-based machine learning methods in order to predict the criticality, not only of network parameters, but also of their bits. Last, dedicated Error Correction Codes (ECCs) are selectively inserted to protect the critical parameters and bits, hence protecting the DNNs with low cost. Thanks to the proposed framework, we explored and protected two Convolutional Neural Networks (CNNs), each with four different data encoding. The results show that it is possible to protect the critical network parameters with selective ECCs while saving up to 83% memory w.r.t. conventional ECC approaches.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128894958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Half Title Page 半页标题

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ets56758.2023.10174071

引用次数: 0

An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds? SRAM FPGA上无保护的RISC-V软核处理器:真的像听起来那么糟糕吗?

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174076

Bruno E. Forlin, Wouter van Huffelen, C. Cazzaniga, P. Rech, Nikolaos S. Alachiotis, M. Ottavi

引用次数: 0

Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning* 基于强化学习的单片3D集成电路电源安全测试点插入方法*

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174135

Shao-Chun Hung, Arjun Chaudhuri, K. Chakrabarty

{"title":"Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning*","authors":"Shao-Chun Hung, Arjun Chaudhuri, K. Chakrabarty","doi":"10.1109/ETS56758.2023.10174135","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174135","url":null,"abstract":"Monolithic 3D (M3D) integration for integrated circuits (ICs) offers the promise of higher performance and lower power consumption over stacked-3D ICs. However, M3D suffers from large power supply noise (PSN) in the power distribution network due to high current demand and long conduction paths from voltage sources to local receivers. Excessive switching activities during the capture cycles in at-speed delay testing exacerbate the PSN-induced voltage droop problem. Therefore, PSN reduction is necessary for M3D ICs during testing to prevent the failure of good chips on the tester (i.e., yield loss). In this paper, we first develop an analysis flow for M3D designs to compute the PSN-induced voltage droop. Based on the analysis results, we extract the test patterns that are likely to cause yield loss. Next, we propose a reinforcement learning (RL)-based framework to insert test points and generate low-switching patterns that help in mitigating PSN without degrading the test coverage. Simulation results for benchmark M3D designs demonstrate the effectiveness of the proposed power-safe testing approach, compared to baseline cases that utilize commercial tools.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121610292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Online Performance Monitoring of Neuromorphic Computing Systems 神经形态计算系统的在线性能监测

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10173860

Abhishek Kumar Mishra, Anup Das, Nagarajan Kandasamy

引用次数: 0

Constraint-Based Automatic SBST Generation for RISC-V Processor Families 基于约束的RISC-V处理器系列SBST自动生成

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174156

Tobias Faller, N. I. Deligiannis, Markus Schwörer, M. Reorda, B. Becker

{"title":"Constraint-Based Automatic SBST Generation for RISC-V Processor Families","authors":"Tobias Faller, N. I. Deligiannis, Markus Schwörer, M. Reorda, B. Becker","doi":"10.1109/ETS56758.2023.10174156","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174156","url":null,"abstract":"Software-Based Self-Tests (SBST) allow at-speed, native online-testing of processors by running software programs on the processor core, requiring no Design for Testability (DfT) infrastructure. The creation of such SBST programs often requires time-consuming manual labour that is expensive and requires in-depth knowledge of the processor’s architecture to target hard-to-test faults. In contrast, encoding the SBST generation task as a Bounded Model Checking (BMC) problem allows using sophisticated, state-of-the-art BMC solvers to automatically generate an SBST. Constraints for the BMC problem are encoded in a circuit called Validity Checker Module (VCM) and applied during SBST generation.In this paper, we focus on presenting a VCM architecture and a constraint set that allows building SBSTs that make minimal assumptions about the firmware, targeting hard-to-test faults in the ALU and register file of multiple scalar, in-order RISC-V processor families. The VCM architecture consists of a processor-specific mapping layer and a generic constraint set connected via a well-defined interface. The generic constraint set enforces the desired SBST behaviour, including controlling the processor’s pipeline state, memory accesses, and with that executed instructions, register state, and fault propagations. Using a generic constraint set allows for rapid SBST generation targeting new RISC-V processor families while keeping the generic constraints untouched. Lastly, we evaluate this approach on two RISC-V processor families, namely the DarkRISCV and a proprietary, industrial core showing the portability and strength of the approach, allowing for rapidly targeting new processors.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128076624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

SET Effects on Quasi Delay Insensitive and Synchronous Circuits 准延迟不敏感和同步电路的SET效应

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10173866

Zaheer Tabassam, A. Steininger

{"title":"SET Effects on Quasi Delay Insensitive and Synchronous Circuits","authors":"Zaheer Tabassam, A. Steininger","doi":"10.1109/ETS56758.2023.10173866","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10173866","url":null,"abstract":"Due to their unbounded data accepting windows asynchronous circuits seem to be more susceptible to environmental effects than their synchronous counterparts with their strict data latching protocol. The technology advancement makes single event transients (SETs) more of a concern towards reliable operation.To better understand the properties of the mentioned classes we present their behaviour under the influence of SETs in a more detailed view that helps to visualize their unseen characteristics. For comparison we propose a way of fault injection where the length of a fault pulse is not fixed, calculated based on maximum gate delay, but related to the circuit's computation steps instead.The analysis concludes that asynchronous quasi delay-insensitive (QDI) circuits show better resilience against SETs due to two main reasons: (1) if realized with a 4-phase handshake protocol they are 95 to 97% resilient to negative fault pulses (2) the susceptibility of a circuit is largely unchanged for increasing fault length because of the causality underlying the QDI principle.Our analysis provides insights leading towards more resilient QDI circuits: if we only make a circuit or specific gates better resist \"1\" faults, we are fully resilient towards the single event transient (SET)s because \"0\" faults are already filtered out by its inherent behaviour. This is also beneficial for area efficiency; as asynchronous circuits often require already double or more area and computation time compared to synchronous circuits, adding extra SET mitigation with double-up or other buffer redundant techniques tends to result in painful overheads. Being able to focus the protection to \"1\" faults, as indicated by our analysis, can hence yield important savings.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115537115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates psc -水印:基于功率侧信道的IP水印使用时钟门

2023 IEEE European Test Symposium (ETS) Pub Date : 2023-05-22 DOI: 10.1109/ETS56758.2023.10174052

Upoma Das, Sazadur Rahman, N. Anandakumar, K. Z. Azar, Fahim Rahman, M. Tehranipoor, Farimah Farahmandi

{"title":"PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates","authors":"Upoma Das, Sazadur Rahman, N. Anandakumar, K. Z. Azar, Fahim Rahman, M. Tehranipoor, Farimah Farahmandi","doi":"10.1109/ETS56758.2023.10174052","DOIUrl":"https://doi.org/10.1109/ETS56758.2023.10174052","url":null,"abstract":"With the ever-increasing re-use of intellectual property (IP) cores in modern system-on-chips (SoCs), it is crucial to prevent security risks such as IP piracy and overuse. Considering that IP watermarking is a potential solution to the copyright protection of IP cores, this paper proposes PSC-Watermark as a power side-channel-based IP authentication methodology using clock gates. PSC-Watermark embeds a power signature with very minimal modification to the IP core. It is done by reusing the existing clock gates to modify the dynamic power consumption inside the IP (in an SoC) based on an applied challenge, and it generates a unique power trace that works as a signature of the IP. Our experimental results show that this power signature can be robustly/effectively verified, even with the interferences emanating from the rest of the functional cores in complex SoCs. We evaluate our technique on several benchmarks of varying size (i.e., MIPS, openMSP430, or1200) in the presence of multiple non-watermarked cores operating in parallel and obtain > 90% confidence rate in proving the ownership of each watermarked IP core. Furthermore, the IP cores are watermarked in a subtle and obfuscated way with < 4% overhead, which makes the proposed technique hard to detect, remove or modify.","PeriodicalId":211522,"journal":{"name":"2023 IEEE European Test Symposium (ETS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127684710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0