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Interactive Shape Generation and Spatial Conflict Testing 交互式形状生成和空间冲突测试
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585335
Y. Kalay
{"title":"Interactive Shape Generation and Spatial Conflict Testing","authors":"Y. Kalay","doi":"10.1109/DAC.1981.1585335","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585335","url":null,"abstract":"A general purpose, research oriented, interactive modeling system is presented. It is based on two different coherent polyhedral shape representations: a planar graph, used for computation and data manipulation, and a relational-database for compact store and general communication with application programs. The two representations effectively partition the system shape-space into active and inactive shapes, respectively. These are explicitly interchangeable by the user, keeping the actual workspace at a manageable size. The basic functionalities provided by the system include the combination of primitive shapes into complex objects by means of spatial set operators (union, intersection and difference), their modeling by means of scaling, rotation and translation, spatial interference detection and graphical display capabilities.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121392195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Low Cost Hierarchical System for VLSI Layout and Verification VLSI布局与验证的低成本分层系统
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585403
T. H. Edmondson, R. M. Jennings
{"title":"A Low Cost Hierarchical System for VLSI Layout and Verification","authors":"T. H. Edmondson, R. M. Jennings","doi":"10.1109/DAC.1981.1585403","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585403","url":null,"abstract":"With IC complexity and the manhour effort required for design doubling every two years, new approaches to layout and mask verification are required. A low-cost VLSI layout and verification system was developed to produce cost effective designs using present resources. The system is IC technology independent, makes effective use of present design skills while maintaining density, and includes structured and behavioral intelligence to aid design verification. In addition, it is easy to learn to use since it provides a simplified design methodology for layout.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116235945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Generation of Technical Data Drawing Packages by the Integration of Design Automation Graphics 设计自动化图形集成技术数据绘图包的生成
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585418
H. N. Lerman
{"title":"The Generation of Technical Data Drawing Packages by the Integration of Design Automation Graphics","authors":"H. N. Lerman","doi":"10.1109/DAC.1981.1585418","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585418","url":null,"abstract":"Martin Marietta Data Systems is designing and implementing for Martin Marietta Orlando Aerospace, a major defense contractor, a system to computerize and integrate all unclassified CAD/CAM graphic outputs related to a large defense project. The system provides for the computerized generation of a Technical Data Package (TDP) containing all of the drawings, standards, and specifications generated during the research and development phase of product design. The heart of the system is a \"vault\" of computer-contained text and drawing data bases which replace present hardcopy vaults. The system also replaces the present manual search and reproduction of drawings with computer inquiry and on-line graphics viewing capabilities. It is expected that the time required to produce the TDP will be cut from several months to a few weeks.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114532946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Integrated Computer Aided Design System for Gate Array Masterslices: Part 2 The Layout Design System Mars-M3 门阵列母片集成计算机辅助设计系统:第二部分Mars-M3布局设计系统
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585450
C. Tanaka, S. Murai, Hiroo Tsuji, T. Yahara, K. Okazaki, M. Terai, R. Katoh, Mikio Tachibana
{"title":"An Integrated Computer Aided Design System for Gate Array Masterslices: Part 2 The Layout Design System Mars-M3","authors":"C. Tanaka, S. Murai, Hiroo Tsuji, T. Yahara, K. Okazaki, M. Terai, R. Katoh, Mikio Tachibana","doi":"10.1109/DAC.1981.1585450","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585450","url":null,"abstract":"Described are the outline and the application results of a fully automatic chip layout design system which has been utilized for years for the development of over a hundred options of ECL and MOS gate arrays. The features and techniques of the placement, routing and checking subsystems as well as the chip layout model which can be treated by the system are discussed.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128475614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Circuit Recognition and Verification Based on Layout Information 基于布局信息的电路识别与验证
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585427
I. Ablasser, U. Jäger
{"title":"Circuit Recognition and Verification Based on Layout Information","authors":"I. Ablasser, U. Jäger","doi":"10.1109/DAC.1981.1585427","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585427","url":null,"abstract":"The mathematical and technical background information for our highly efficient procedure of circuit recognition and verification from layout information is presented. Complete verification and extremely short computing times are the main goals. This procedure can be performed for bipolar as well as for MOS technologies and is part of the whole layout-control system LOCATE.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128516942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A MOS/LSI Oriented Logic Simulator 一个MOS/LSI导向的逻辑模拟器
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585364
D. Holt, D. Hutchings
{"title":"A MOS/LSI Oriented Logic Simulator","authors":"D. Holt, D. Hutchings","doi":"10.1109/DAC.1981.1585364","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585364","url":null,"abstract":"A logic simulator capable of efficiently modelling complex MOS/LSI circuits is presented. The circuit is simulated at the combinational logic and transmission gate level using a set of six node-states. Gate models have inertial delay and assignable nominal rise and fall delays. Both unidirectional and bidirectional transmission gates are accurately simulated, and functional models are provided for ROM, RAM, etc.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"283 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122958160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A Totally Integrated Systems Approach to Design and Manufacturing at McDonnell Douglas Corporation 麦道公司设计与制造的完全集成系统方法
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585347
M. Mills
{"title":"A Totally Integrated Systems Approach to Design and Manufacturing at McDonnell Douglas Corporation","authors":"M. Mills","doi":"10.1109/DAC.1981.1585347","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585347","url":null,"abstract":"During the 1970s, industry in the United States lost $125 billion of potential production and at least 2 million jobs. Between 1948 and 1968 U.S. output per hour worked increased at an annual rate of 3.2%. For the past seven years this has dropped to 0.7%. This dramatic downturn in the industrial economy is largely due to a widespread decline in productivity. McDonnell Douglas Corporation (MDC) has addressed the issue of productivity by integrating CAD/CAM technology into its design and manufacturing components.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123521261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic Input and Interactive Editing Systems of Logic Circuit Diagrams 逻辑电路图自动输入与交互编辑系统
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585421
M. Ishii, Yoshikazu Ito, M. Iwasaki, Masanari Yamamoto, S. Kodama
{"title":"Automatic Input and Interactive Editing Systems of Logic Circuit Diagrams","authors":"M. Ishii, Yoshikazu Ito, M. Iwasaki, Masanari Yamamoto, S. Kodama","doi":"10.1109/DAC.1981.1585421","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585421","url":null,"abstract":"This paper discusses automatic input and interactive editing systems of logic circuit diagrams. Automatic input is based on pattern recognition, and interactive editing is executed through a graphic display. The system is implemented on a FACOM M-180 II and a PANAFACOM U-400. System overview, hardware configuration, pattern recognition algorithms, editing system, data-base, as well as current results are described.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124007478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Functional Level Simulation in FANSIM3 - Algorithms, Data Structures and Results FANSIM3中的功能级仿真——算法、数据结构和结果
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585359
S. Hirschhorn, M. Hommel, C. Bures
{"title":"Functional Level Simulation in FANSIM3 - Algorithms, Data Structures and Results","authors":"S. Hirschhorn, M. Hommel, C. Bures","doi":"10.1109/DAC.1981.1585359","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585359","url":null,"abstract":"This paper discusses the functional level logic simulation techniques used in the FANSIM3 simulator. The data structures for function evaluation and the algorithms used to simulate functional models are presented. The methods used to simulate datapaths and bussed signals are also discussed. Specific results, based on a year's experience with the simulator, are presented.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122566923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A Statistical Model for Net Length Estimation 网长估计的统计模型
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585444
L. Suen
{"title":"A Statistical Model for Net Length Estimation","authors":"L. Suen","doi":"10.1109/DAC.1981.1585444","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585444","url":null,"abstract":"The prerouting estimation of net length is very important to the physical design since the estimated length can be employed as a figure-of-merit of the placement process, as an evaluation of the placement result, and in the calculation of capacitance in the predictive timing analysis. The traditional methods, bounded rectangle method, minimal spanning tree method and minimal Steiner tree method, result in either poor estimation or time consuming processing. Moreover, they do not consider the interference between each net and the technology influence. A statistical model for net length estimation has been developed to overcome these deficiencies. This model provides an unbiased estimate with 7 percent relative root-mean-squares error on an average.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122901645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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