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18th Design Automation Conference最新文献

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Survey of Analysis, Simulation and Modeling for Large Scale Logic Circuits 大型逻辑电路的分析、仿真与建模综述
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585342
A. Ruehli
{"title":"Survey of Analysis, Simulation and Modeling for Large Scale Logic Circuits","authors":"A. Ruehli","doi":"10.1109/DAC.1981.1585342","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585342","url":null,"abstract":"The purpose of this paper is to introduce recent developments in the time analysis, simulation and modeling of logic circuits. These advances which have taken place in the circuit and systems area augment the recent advances in logic time simulators. The latest trend has been to combine the approaches into a single system, a so called mixed simulation-analysis program. In this paper we review some of the circuit oriented techniques at a level understandable to the non circuit-theorist.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121970268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Random Fault Analysis 随机故障分析
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585382
R. M. McDermott
{"title":"Random Fault Analysis","authors":"R. M. McDermott","doi":"10.1109/DAC.1981.1585382","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585382","url":null,"abstract":"A method is presented for performing rapid Test Pattern Evaluation (TPE) using classical statistical analysis. This method is applicable regardless of the types of faults being considered, the likelihood of the fault occuring, or the technique used for fault simulation. A subset of the complete fault list is selected using random sampling techniques, and the fault coverage (percentage of faults detectable by the given test pattern) is estimated and confidence limits about this estimate are given. This technique is useful for LSI as well as VLSI Test Pattern Evaluation in that only a small subset of the total fault list need be analyzed to determine the fault coverage within a few percent.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126665786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A MOS Modelling Technique for 4-State True-Value Hierarchical Logic Simulation or Karnough Knowledge 四态真值层次逻辑仿真或Karnough知识的MOS建模技术
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585445
W. Sherwood
{"title":"A MOS Modelling Technique for 4-State True-Value Hierarchical Logic Simulation or Karnough Knowledge","authors":"W. Sherwood","doi":"10.1109/DAC.1981.1585445","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585445","url":null,"abstract":"Modelling strategies and techniques are given for static and dynamic MOS transistors in a 4--state (0/low, 1/high, Z/high-impedance, U/undefined) logic simulator environment. General MOS modelling problems are presented and a set of workable solutions are developed. Experience with these techniques is shown along with examples of NMOS simulation applications. This paper discusses a technique with specific conventions for modelling MOS devices at the \"logical transistor\" gate level. The technique is not the optimal general solution, but was found to be satisfactory for retrofitting an existing 4--state logic simulator to include MOS capabilities. The technique is not meant to replace analog circuit simulation, but is aimed at increasing the accuracy of MOS logic (gate level) simulations. We begin with a general bus model and extend it to handle transistors, pullups and pulldowns, and dynamic MOS transfer gates. Extensions are shown for a bidirectional transfer gate model that can be connected in any topological configuration.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125492749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Test Data Verification - Not Just the Final Step for Test Data before Release for Production Testing 测试数据验证-不仅仅是生产测试发布前测试数据的最后一步
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585458
Peter Solecky, R. L. Panko
{"title":"Test Data Verification - Not Just the Final Step for Test Data before Release for Production Testing","authors":"Peter Solecky, R. L. Panko","doi":"10.1109/DAC.1981.1585458","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585458","url":null,"abstract":"Increased product complexity has touched all aspects of testing: hardware, software, and procedures. The test data verification process is not immune to this increased complexity. Qualification, validation, and final inspection of the test data prior to its acceptance for use in production testing of printed circuit boards has matured to a science. Large test data volumes, circuit density, technology mixing, sophisticated testers, as well as the extensive product development process, have all contributed to this complexity. Recently, major emphasis and attention have been focused on this critical process. This paper explores the underlying problems associated with traditional test data verification. An effective approach, environment, and total strategy are proposed to deal with the test data verification challenge.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130542669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On Logic Comparison 论逻辑比较
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585455
L. Berman
{"title":"On Logic Comparison","authors":"L. Berman","doi":"10.1109/DAC.1981.1585455","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585455","url":null,"abstract":"This report deals with the problem of discovering the differences between two implementations of the same partially specified function. It describes a heuristic approach to the boolean equivalence problem which yields information important for understanding structural differences. It also contains a formalization for the notion of \"structural difference\" and presents an algorithm for approximating this difference.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129604496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
AIDE - A Tool for Computer Architecture Design 计算机体系结构设计工具
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585448
D. J. Ellenberger, Ying W. Ng
{"title":"AIDE - A Tool for Computer Architecture Design","authors":"D. J. Ellenberger, Ying W. Ng","doi":"10.1109/DAC.1981.1585448","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585448","url":null,"abstract":"AIDE (ArchItecture Design Environment) is a modeling and simulation system designed to support the development of computer architectures. By providing a modular, hierarchical modeling environment plus interactive simulation and performance evaluation capabilities, AIDE facilitates the critical analysis necessary in top-down architecture designs. The system currently runs under the UNIX operating system on a VAX 11/780. This paper presents the organization of AIDE and discusses its application to computer architecture design.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132955994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Automatic Placement of Rectangular Blocks with the Interconnection Channels 具有互连通道的矩形块的自动放置
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585390
R. Malladi, G. Serrero, A. Verdillon
{"title":"Automatic Placement of Rectangular Blocks with the Interconnection Channels","authors":"R. Malladi, G. Serrero, A. Verdillon","doi":"10.1109/DAC.1981.1585390","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585390","url":null,"abstract":"This paper describes a placement method of rectangular blocks with the interconnection channels. The method consists of a constructive initial placement followed by an iterative improvement. An estimation of the interconnection channel widths, the number of crossovers and the connection lengths is proposed. The criteria to be minimized are : area, number of crossovers and connection length.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114196025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Structured Approach to Selecting a CAD/CAM System 选择CAD/CAM系统的结构化方法
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.5555/800073.802378
R. I. McNall, R. D'Innocenzo
{"title":"A Structured Approach to Selecting a CAD/CAM System","authors":"R. I. McNall, R. D'Innocenzo","doi":"10.5555/800073.802378","DOIUrl":"https://doi.org/10.5555/800073.802378","url":null,"abstract":"","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128154378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MOSSIM: A Switch-Level Simulator for MOS LSI MOS大规模集成电路的开关级模拟器
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1145/62882.62933
R. Bryant
{"title":"MOSSIM: A Switch-Level Simulator for MOS LSI","authors":"R. Bryant","doi":"10.1145/62882.62933","DOIUrl":"https://doi.org/10.1145/62882.62933","url":null,"abstract":"The logic simulator MOSSIM is designed specifically to serve the needs of the MOS LSI designer. It models a MOS circuit as a network of field-effect transistor \"switches\", with node states 0, 1, and X (unknown) and transistor states \"open\", \"closed\", and \"unknown\". MOSSIM has proved quite versatile and accurate in simulating a variety of MOS designs including ones for which the network was extracted automatically from the mask specifications. Because it models the network at a logical level, it has a performance comparable to conventional logic gate simulators.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121062393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 80
Automatic Generation and Characterization of CMOS Polycells CMOS多晶元的自动生成与表征
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585355
C. M. Lee, B. Chawla, S. Just
{"title":"Automatic Generation and Characterization of CMOS Polycells","authors":"C. M. Lee, B. Chawla, S. Just","doi":"10.1109/DAC.1981.1585355","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585355","url":null,"abstract":"With increasing complexity and size of integrated circuits, computer aids for layout and simulation have begun to play an ever-increasing role. An approach to take advantage of these aids is the polycell design approach. However, thus far, manual procedures have been used in creating the interior of polycells. A layout style in which CMOS technology lends itself to automation and design rule updatability has been found and is described here. A program has been implemented which takes as input a symbolic description of polycells and a set of design rules, and outputs a mask description of polycells. This mask description and a command file are then input to a layout characterization and verification software system to automatically generate inputs for a polycell layout system, a circuit simulator, and a timing simulator.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121137281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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