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Some Properties of a Probabilistic Model for Global Wiring 全局布线概率模型的若干性质
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585424
D. Wallace, L. Hemachandra
{"title":"Some Properties of a Probabilistic Model for Global Wiring","authors":"D. Wallace, L. Hemachandra","doi":"10.1109/DAC.1981.1585424","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585424","url":null,"abstract":"A probabilistic model is developed to study the process of automatic global wiring for LSI and VLSI chips. The probability parameter for this model is related to the local utilization rate and the channel supply on each global cell boundary. This theoretical relationship is compared with a real example, which agrees well with the theoretical prediction. Using Monte Carlo methods to obtain numerical solutions from the model, the effects of search region size on global routing probability are studied. There seems to be little gain in going more than one or two global cells beyond the minimum rectangle to find a path, regardless of the length of the connection. This conclusion is supported by the observation that the routing probability does not \"scale\" very accurately as the dimensions of the problem are increased.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123044739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On Proving the Correctness of Optimizing Transformations in a Digital Design Automation System 数字设计自动化系统优化转换正确性论证
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585337
M. C. McFarland
{"title":"On Proving the Correctness of Optimizing Transformations in a Digital Design Automation System","authors":"M. C. McFarland","doi":"10.1109/DAC.1981.1585337","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585337","url":null,"abstract":"As part of our research for the Carnegie-Mellon University Design Automation System, we have been investigating methods for proving that the system produces correct designs from correct specifications. This paper presents a mathematical model of the behavior of hardware descriptions which has been used to prove that some of the optimizing transformations applied to abstract hardware descriptions in the system preserve behavioral equivalence. The model goes beyond the usual computational models used in program verification in that it takes into account the proper sequencing of \"events\" which represent interactions with the environment.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"2018 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125739011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A CAD System for Logic Design Based on Frames and Demons 基于框架与图形的逻辑设计CAD系统
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585394
Takao Saito, T. Uehara, N. Kawato
{"title":"A CAD System for Logic Design Based on Frames and Demons","authors":"Takao Saito, T. Uehara, N. Kawato","doi":"10.1109/DAC.1981.1585394","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585394","url":null,"abstract":"A hierarchical logic design system based on frames and demons is proposed in this paper. Featuring a graphic editor which puts the design information into frames and a symbolic simulator which consists of demons (data-driven functions stored in frames), the system is flexible enough for a designer to easily add his own functions, such as monitoring functions of design constraints.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114890619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A Simulator to Replace Wire Rules for High Speed Computer Design 一种取代线路规则的高速计算机设计模拟器
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585340
Adrian Hlynka
{"title":"A Simulator to Replace Wire Rules for High Speed Computer Design","authors":"Adrian Hlynka","doi":"10.1109/DAC.1981.1585340","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585340","url":null,"abstract":"Signal quality is of great concern on PC boards containing high speed logic. Improper positioning of loads in a network can cause reflection problems. Traditionally engineers have dealt with this by imposing wire rules on the layout process. The use of simulators during layout can be more accurate and less restrictive than wire rules. To make this possible, the simulator must not only simulate reflection noise but determine how to add the minimum amount of etch to solve the reflection problem. A unique algorithm that does this is described here.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122419993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design Automation Status in Japan 日本设计自动化现状
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585330
A. Yamada
{"title":"Design Automation Status in Japan","authors":"A. Yamada","doi":"10.1109/DAC.1981.1585330","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585330","url":null,"abstract":"This paper surveys the Japanese design automation (DA) status and activities. First, the DA statistics for major Japanese organizations are presented. These statistics show the status of logic, physical and test DA for digital systems and LSIs. Second, notable DA activities of Japanese manufacturers, laboratories and universities are introduced.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114408271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
User Documentation for Design Automation at TI 用户文档的设计自动化在TI
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585419
D. M. Sims, J. Crabbe
{"title":"User Documentation for Design Automation at TI","authors":"D. M. Sims, J. Crabbe","doi":"10.1109/DAC.1981.1585419","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585419","url":null,"abstract":"The use of documentation in design automation is extensive. The \"DADGUIDE\" Documentation System at Texas Instruments' Design Automation Department accomplishes many documentation tasks by means of a set of procedures, local and central computers, word processing programs with macro capabilities, and physical text formatters. The documentation output is resident on a data set at the central computing facility. When users request documents through submission of batch jobs, they execute a document printing program which outputs user manuals at any terminal in line printer, microfiche, or LASER copy. Control over the style and content of such user documentation is achieved by restrictions on characters and symbols, macro commands which force numbered divisions and subdivisions, procedures for revision of documents, check programs verifying output of the DADGUIDE processors, and requirements for approval of the documentation. In these ways, the DADGUIDE system is automating the management of user documentation and helping to extend the use of computer-aided tools company-wide.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117330881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Perspective View of the MODCON System MODCON系统的透视
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585350
Y. K. Chan
{"title":"A Perspective View of the MODCON System","authors":"Y. K. Chan","doi":"10.1109/DAC.1981.1585350","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585350","url":null,"abstract":"In this paper, a system of computer programs for the geometric description of hot forgings is outlined. The system is known as the MODCON system which stands for MODular CONstruction. The MODCON system allows quite complex forging shapes to be produced from relatively few input instructions. The forging geometry is defined as a series of volumetric modules which are then merged together during generation of the N.C. tape necessary to machine the finishing-cut EDM electrode for the whole forging cavity. The system can also be used for the roughing cut of the EDM electrode before the finishing cut stage as well as for generating cross-sectional data which serves as input to subsequent preform design systems. The system represents a considerable saving in time and cost over current methods involving conventional pattern making for the copy milling of electrodes.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129323681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ABLE: A LISP-Based Layout Modeling Language with User-Definable Procedural Models for Storage/Logic Array Design 基于lisp的布局建模语言，具有用户可定义的过程模型，用于存储/逻辑阵列设计
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585370
G. B. Goates, S. Patil
{"title":"ABLE: A LISP-Based Layout Modeling Language with User-Definable Procedural Models for Storage/Logic Array Design","authors":"G. B. Goates, S. Patil","doi":"10.1109/DAC.1981.1585370","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585370","url":null,"abstract":"ABLE, an array-based linguistic editor, is a layout modeling language for storage/logic arrays (SLA's) that is based on the LISP programming language. This paper describes ABLE's design, presents an ABLE layout program, and evaluates ABLE's usefulness in SLA-based circuit design. ABLE embodies a linguistic approach to computer-aided design (CAD) for very large scale integrated (VLSI) circuits; digital system designers can represent SLA-based integrated circuits as relatively abstract and highly flexible ABLE layout programs. The informational complexity of VLSI design can be reduced both by using straightforward CAD algorithms based on the SLA structured logic layout technique, and by using user-definable procedural models within LISP-based layout modeling languages.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"41 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120902630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PRIMEAIDS: An Integrated Electrical Design Environment 一个集成的电气设计环境
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585420
Roger K. Cleghorn
{"title":"PRIMEAIDS: An Integrated Electrical Design Environment","authors":"Roger K. Cleghorn","doi":"10.1109/DAC.1981.1585420","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585420","url":null,"abstract":"PRIMEAIDS is a CAD system that provides a total interactive command environment for electrical engineers, draftsmen, and technicians. It integrates the many computer tools that are needed to increase productivity and accuracy of producing electronic products. PRIMEAIDS provides interfaces to major CAD tools such as simulation, wire-wrap generation, and PCB and LSI layout in a way that is consistent to the designer; making all of these tools appear as a single, integrated system.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116327126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
PODEM-X: An Automatic Test Generation System for VLSI Logic Structures 超大规模集成电路逻辑结构自动测试生成系统
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1145/62882.62931
P. Goel, Barry C. Rosales
{"title":"PODEM-X: An Automatic Test Generation System for VLSI Logic Structures","authors":"P. Goel, Barry C. Rosales","doi":"10.1145/62882.62931","DOIUrl":"https://doi.org/10.1145/62882.62931","url":null,"abstract":"Multiple test generation algorithms and techniques described in this paper have been integrated into a unified system which has successfully produced tests for unpartitioned LSSD logic structures of up to 50,000 logic gates. The design concepts behind the creation of a unified system are presented, as are actual results obtained on large logic structures. System usability was significantly enhanced by the same concepts that facilitated the integration of multiple algorithms and techniques.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116481192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 99
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