{"title":"Bolt - A Block Oriented Design Specification Language","authors":"D. Holt, S. Sapiro","doi":"10.1109/DAC.1981.1585363","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585363","url":null,"abstract":"BOLT is a block-oriented MOS Integrated Circuit design language which relies heavily on macro, define, and parameter default features in order to simplify the design specification. A compiler generates block, logic, and transistor level equivalents used in an integrated CAD system including logic simulators, timing verification, place and route software and other packages. To handle the rapidly changing custom MOS/LSI environment the device types are defined externally to the compiler.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114929013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Combining Graphics and a Layout Language in a Single Interactive System","authors":"S. Trimberger","doi":"10.1109/DAC.1981.1585357","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585357","url":null,"abstract":"Layout languages provide users with the capability to algorithmically define cells. But the specification language is so non-intuitive that it is impossible to debug a design in that language, one must plot it. Interactive graphics systems, on the other hand, allow the user to debug in the form in which he sees the design, but severely restrict the language he may use to express the graphics. For example, he cannot express loops or conditionals. What is really needed is a single interactive system that combines layout language and graphic modifications to the data. This paper describes just such a system.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126735600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Optimum Layer Assignment for Routing in ICs and PCBs","authors":"M. Ciesielski, E. Kinnen","doi":"10.1109/DAC.1981.1585439","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585439","url":null,"abstract":"An optimum layer assignment of interconnections in IC and two-layer PCB is derived. The assignment is optimal in the sense that it is achieved through a global minimization of contacts or vias. The problem is formulated as a 0,1 integer program and solved using a branch and bound technique. There are no constraints on contact location or on the number of wires that can be connected at each contact. Applications of this procedure to VLSI circuits are discussed.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122690881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Parallel Bit Map Processor Architecture for DA Algorithms","authors":"T. Blank, M. Stefik, W. M. V. Cleemput","doi":"10.1109/DAC.1981.1585453","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585453","url":null,"abstract":"Bit maps have been used in many Design Automation (DA) algorithms such as printed circuit board (PCB) layout and integrated circuit (IC) design rule checking (DRC). The attraction of bit maps is that they provide a direct representation of two-dimensional images. The difficulty with large scale use of bit maps (e.g., for DRC on VLSI) is that the large amounts of data can consume impractical amounts of computation on sequential machines. This paper describes a processing architecture that is specifically designed to operate on bit maps. It has an inherently two-dimensional construction and has a very large parallel processing capability. Also included in this paper are descriptions of algorithms that exploit the architecture. Algorithms for routing, DRC, and bit vector manipulation are included.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127541766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"LSI Product Quality and Fault Coverage","authors":"V. Agrawal, S. Seth, P. Agrawal","doi":"10.1145/62882.62930","DOIUrl":"https://doi.org/10.1145/62882.62930","url":null,"abstract":"At present, the relationship between fault coverage of LSI circuit tests and the tested product quality is not satisfactorily understood. Reported work on integrated circuits predicts, for an acceptable field reject rate, a fault coverage that is too high (99 percent or higher). This fault coverage is difficult to achieve for LSI circuits. This paper proposes a model of fault distribution for a chip. The number of faults on a defective chip is assumed to have a Poisson density for which the average value is determined through experiment on actual chips. The procedure, which relates the model to the chip being studied, is simple; one or more fabricated chip lots must be tested by a few preliminary test patterns. Once the model is characterized, the required value of fault coverage can be easily determined for any given field reject rate. The main advantage of such a model is that it adapts itself to the various characteristics of the chip (technology, feature size, manufacturing environment, etc.) and the fault model (e.g., stuck-type faults). As an example, the technique was applied to an LSI circuit; realistic results were obtained.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130903246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Partitioning for VLSI Placement Problems","authors":"Arvind M. Patel, L. C. Cote","doi":"10.5555/800073.802337","DOIUrl":"https://doi.org/10.5555/800073.802337","url":null,"abstract":"Two partition/interchange processes are described for solving VLSI placement problems. Explicit partitioning is used in both methods to decompose the initial large graph into several smaller graphs for initial placement and subsequent interchange optimization. Comparative runs were made between the two processes and against the interchange process without partitioning on problems involving a few hundred elements. The comparative results clearly establish the effectiveness of partitioning in enhancing the performance of interchange processes and constraining computation time growth. While the two methods described herein were developed for VLSI placement problems, they are applicable to quadratic assignment problems arising from numerous other settings.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128774037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Kamikawai, M. Yamada, T. Chiba, K. Furumaya, Yoji Tsuchiya
{"title":"A Critical Path Delay Check System","authors":"R. Kamikawai, M. Yamada, T. Chiba, K. Furumaya, Yoji Tsuchiya","doi":"10.1109/DAC.1981.1585341","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585341","url":null,"abstract":"A Critical Path Delay Check System for designing computers is described. It calculates the critical path delay between the start and end points. It can be used in the early stage of design when, for example, the location of the components on a plug-in card has not yet been determined. Some algorithms for predicting delays are also introduced.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133570766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Verification and Optimization for LSI & PCB Layout","authors":"H. N. Brady, R.J. Smith","doi":"10.1109/DAC.1981.1585383","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585383","url":null,"abstract":"Layout optimization involves interconnection wiring modifications, which improve aesthetic appearance, fabrication characteristics, routability, and reliability of routed boards/chips. Requirements and capabilities of a general purpose layout optimizer are presented, then organization and processing flow of the program are outlined. The functional decomposition and modular structure of this system are presented. Results achieved by using the verifier/optimizer on large printed circuit boards and gate arrays are given.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123163581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Sakauye, A. Lubiw, J. Royle, R. Epplett, Jeffrey Tweedale, E. S. Shew, E. Attfield, F. Brglez, P. Wilcox
{"title":"A Set of Programs for MOS Design","authors":"G. Sakauye, A. Lubiw, J. Royle, R. Epplett, Jeffrey Tweedale, E. S. Shew, E. Attfield, F. Brglez, P. Wilcox","doi":"10.1109/DAC.1981.1585392","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585392","url":null,"abstract":"A set of programs used in the design of custom hand packed and standard cell MOS circuits is described. The programs cover logic simulation, filter analysis, circuit simulation, timing simulation, circuit extraction from layout, design tolerance checking, connectivity checking and user interface facilities. A cell documentation system is used to tie together the various design support packages.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134014170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Software Engineering Applied to Computer-Aided Design (CAD) Software Development","authors":"Dan C. Nash, H. Willman","doi":"10.1109/DAC.1981.1585407","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585407","url":null,"abstract":"This paper briefly discusses software engineering and its relationship to CAD. We look at:\u0000 • software engineering and the software life cycle\u0000 • the characteristics of CAD software\u0000 • a survey of software engineering use in CAD\u0000 • recommendations for the use of software tools in CAD\u0000 • recommendations for the development of new software engineering techniques to aid the CAD developer.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134043427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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