{"title":"大规模集成电路的验证与优化PCB布局","authors":"H. N. Brady, R.J. Smith","doi":"10.1109/DAC.1981.1585383","DOIUrl":null,"url":null,"abstract":"Layout optimization involves interconnection wiring modifications, which improve aesthetic appearance, fabrication characteristics, routability, and reliability of routed boards/chips. Requirements and capabilities of a general purpose layout optimizer are presented, then organization and processing flow of the program are outlined. The functional decomposition and modular structure of this system are presented. Results achieved by using the verifier/optimizer on large printed circuit boards and gate arrays are given.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Verification and Optimization for LSI & PCB Layout\",\"authors\":\"H. N. Brady, R.J. Smith\",\"doi\":\"10.1109/DAC.1981.1585383\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Layout optimization involves interconnection wiring modifications, which improve aesthetic appearance, fabrication characteristics, routability, and reliability of routed boards/chips. Requirements and capabilities of a general purpose layout optimizer are presented, then organization and processing flow of the program are outlined. The functional decomposition and modular structure of this system are presented. Results achieved by using the verifier/optimizer on large printed circuit boards and gate arrays are given.\",\"PeriodicalId\":201443,\"journal\":{\"name\":\"18th Design Automation Conference\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1981-06-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"18th Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1981.1585383\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"18th Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1981.1585383","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Verification and Optimization for LSI & PCB Layout
Layout optimization involves interconnection wiring modifications, which improve aesthetic appearance, fabrication characteristics, routability, and reliability of routed boards/chips. Requirements and capabilities of a general purpose layout optimizer are presented, then organization and processing flow of the program are outlined. The functional decomposition and modular structure of this system are presented. Results achieved by using the verifier/optimizer on large printed circuit boards and gate arrays are given.
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