LSI Product Quality and Fault Coverage

V. Agrawal, S. Seth, P. Agrawal
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引用次数: 25

Abstract

At present, the relationship between fault coverage of LSI circuit tests and the tested product quality is not satisfactorily understood. Reported work on integrated circuits predicts, for an acceptable field reject rate, a fault coverage that is too high (99 percent or higher). This fault coverage is difficult to achieve for LSI circuits. This paper proposes a model of fault distribution for a chip. The number of faults on a defective chip is assumed to have a Poisson density for which the average value is determined through experiment on actual chips. The procedure, which relates the model to the chip being studied, is simple; one or more fabricated chip lots must be tested by a few preliminary test patterns. Once the model is characterized, the required value of fault coverage can be easily determined for any given field reject rate. The main advantage of such a model is that it adapts itself to the various characteristics of the chip (technology, feature size, manufacturing environment, etc.) and the fault model (e.g., stuck-type faults). As an example, the technique was applied to an LSI circuit; realistic results were obtained.
LSI产品质量和故障覆盖率
目前,人们对LSI电路测试的故障覆盖率与被测产品质量之间的关系还没有很好的认识。集成电路的报告工作预测,对于可接受的现场废品率,故障覆盖率过高(99%或更高)。这种故障覆盖对于大规模集成电路是很难实现的。本文提出了一种芯片故障分布模型。假定缺陷芯片上的故障数具有泊松密度,其平均值通过在实际芯片上的实验确定。将模型与所研究的芯片联系起来的过程很简单;一个或多个制造芯片批次必须通过一些初步测试模式进行测试。一旦模型被表征,对于任何给定的现场拒绝率,可以很容易地确定所需的故障覆盖率值。该模型的主要优点是能够适应芯片的各种特性(工艺、特征尺寸、制造环境等)和故障模型(如卡式故障)。作为一个例子,该技术应用于一个大规模集成电路;得到了比较真实的结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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