发布求助
文献互助 智能选刊 最新文献

18th Design Automation Conference最新文献

筛选
英文 中文
Custom VLSI Electrical Rule Checking in an Intelligent Terminal 智能终端中自定义VLSI电气规则检查
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585429
L. V. Corbin
{"title":"Custom VLSI Electrical Rule Checking in an Intelligent Terminal","authors":"L. V. Corbin","doi":"10.1109/DAC.1981.1585429","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585429","url":null,"abstract":"An extension to a language-based custom VLSI design approach is proposed in which the designer supplies just enough up-front semantic information to allow a substantial amount of beneficial design consistency checking with a minimum of computation. The computational load is reduced by using a bottom-up hierarchical design approach, with incremental checking as the design is built. The load is also reduced by imposing minor restrictions upon the layout designer, by requiring that all active elements be prechecked, and by attaching \"type\" attributes to interconnecting signals. The method is very efficient for highly \"regular\" designs. Checks performed are geometrical design rules, connectivity, static electrical consistency, and node rise-and-fall times.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121573843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Mechanical Design Automation in IBM Poughkeepsie IBM Poughkeepsie机械设计自动化
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585348
Gilbert W. Curl
{"title":"Mechanical Design Automation in IBM Poughkeepsie","authors":"Gilbert W. Curl","doi":"10.1109/DAC.1981.1585348","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585348","url":null,"abstract":"The IBM Poughkeepsie mechanical design system reduces the cost and time to design and release mechanical parts during the product development cycle. The system uses an interactive graphics design program, CADAM (FOOTNOTE: CADAM is a registered trademark of Lockheed Corporation.), and integrates complementary applications driven from the common mechanical design data base. The applications include: 1. Synchronization of the graphics data base with the bill of material data base. 2. Automated power cabling design and checking. 3. Release of mechanical designs using a computer network.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121966725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Contrasts in Physical Design between LSI and VLSI 大规模集成电路和超大规模集成电路物理设计的对比
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585426
W. Heller
{"title":"Contrasts in Physical Design between LSI and VLSI","authors":"W. Heller","doi":"10.1109/DAC.1981.1585426","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585426","url":null,"abstract":"In the last five years, there has been rapid growth in logic and memory chip circuit density. The number of different digital processors and the typical size of such processors has also grown. With all this growth, alternatives in VLSI design style as well as packaging have to be considered. These consist, on the one hand, of powerful automated placement and wiring routines, indispensable on large regular package images, and, on the other, of techniques facilitating rapid, interactive adaptation of functional logic design to the layout and interconnection of \"macros\" on large chips. Some results from study of each method are presented.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126283507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic Generation of Cells for Recurrence Structures 递归结构细胞的自动生成
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585368
Avinoam Bilgory, D. Gajski
{"title":"Automatic Generation of Cells for Recurrence Structures","authors":"Avinoam Bilgory, D. Gajski","doi":"10.1109/DAC.1981.1585368","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585368","url":null,"abstract":"This paper describes a method for automatic translation of functional into structural descriptions for Boolean recurrence systems. The solution of a recurrence system is accomplished by a network that requires at most four different types of cells. Given any Boolean recurrence of any order, the cell generator module defines the Boolean equations of these cells.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126618170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
PAS-LOP: An Automatic Module Location System for PWB PAS-LOP:一种PWB模块自动定位系统
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585346
G. Odawara, Kazuhiko Iijima, N. Ichihara, T. Kiyomatsu
{"title":"PAS-LOP: An Automatic Module Location System for PWB","authors":"G. Odawara, Kazuhiko Iijima, N. Ichihara, T. Kiyomatsu","doi":"10.1109/DAC.1981.1585346","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585346","url":null,"abstract":"In this paper, an automatic module location system for Printed Wiring Boards (PWB's) is discussed. This system is named LOP (LOcation Processor) and is a subsystem of PAS (Packaging Automation System) which is a total design system for PWB's. The most important feature of the LOP is an objective function settled for optimizing the module location. This optimization aims at both the minimum of total wire length and the uniformly distributed wire. And these factors are indispensable for getting a good location for both the automatic routing process and the PWB manufacturing process. By several experiments, the routing efficiency has been improved and good wiring patterns have been acquired with an automatic routing program.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131239752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Graphics Language / One IBM Corporate-Wide Physical Design Data Format 图形语言/一种IBM公司范围的物理设计数据格式
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585436
David R. Lambert
{"title":"Graphics Language / One IBM Corporate-Wide Physical Design Data Format","authors":"David R. Lambert","doi":"10.1109/DAC.1981.1585436","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585436","url":null,"abstract":"The evolution and structure of the IBM Corporate-Wide physical design data language, GL/1 (Graphics Language / One), is discussed. The need for a common graphics interface for communication among various design automation programs is demonstrated. At IBM, the same format is used from physical layout to mask generation for integrated circuit and printed circuit board designs.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"46 40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133245419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Computation of Power Supply Nets in VLSI Layout 超大规模集成电路布局中供电网络的计算
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585329
H. Rothermel, D. Mlynski
{"title":"Computation of Power Supply Nets in VLSI Layout","authors":"H. Rothermel, D. Mlynski","doi":"10.1109/DAC.1981.1585329","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585329","url":null,"abstract":"For a given placement of macrocells with given power consumption a full automatic layout of power supply and ground nets has been developped. The varying width in different segments of these nets is calculated from local current values resulting in rectangles presenting the net segments. These rectangles are embedded in the routing plane with regard to given design rules.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121335398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A Design Automation System for Electronic Switching Systems 电子交换系统的设计自动化系统
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585331
T. Hosaka, K. Ueda, H. Matsuura
{"title":"A Design Automation System for Electronic Switching Systems","authors":"T. Hosaka, K. Ueda, H. Matsuura","doi":"10.1109/DAC.1981.1585331","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585331","url":null,"abstract":"This paper describes the development and operation experience of NTT's design automation (DA) system for analog/digital switching systems. The DA system is composed of several subsystems, such as logic design, physical design, documentation and manufacturing data conversion programs, organized around the centralized data base management system. By using this system, hardware standardization and products compatibility among different manufacturers have been achieved. The outlook for the future DA technology is also discussed.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123624152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Algorithms for Multiple-Criterion Design of Microprogrammed Control Hardware 微程序控制硬件的多准则设计算法
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585400
Andrew W. Nagle, A. C. Parker
{"title":"Algorithms for Multiple-Criterion Design of Microprogrammed Control Hardware","authors":"Andrew W. Nagle, A. C. Parker","doi":"10.1109/DAC.1981.1585400","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585400","url":null,"abstract":"This paper describes two algorithms designed to optimize memory size and controller performance for a microprogrammed controller. The algorithms accept two inputs: a set of interconnected registers and logical operators called the data paths, and a control flow graph which describes how these data paths are to be exercised. The Autonomy algorithm identifies data path elements which should be controlled directly from the microword without encoding. This algorithm aids the effectiveness of the subsequent encoding algorithm by eliminating some signals from consideration. A second algorithm, the Attraction algorithm, determines which microoperations will execute in parallel and which will be encoded into separate microinstruction formats. This algorithm accepts a microword width constraint and implements parallel operations in the microcode and the corresponding encoding. Both the parallelism and the encoding are determined by the algorithm. Application of these algorithms to an example, the PDP (FOOTNOTE: PDP is a registered trademark of Digital Equipment Corporation.)-11/40, has produced a control store design 14 percent wider and equal in parallelism to an equivalent portion of the human design.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122747352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
AREA-Time Efficient Addition in Charge Based Technology 基于电荷的区域-时间效率加法技术
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585456
R. Montoye
{"title":"AREA-Time Efficient Addition in Charge Based Technology","authors":"R. Montoye","doi":"10.1109/DAC.1981.1585456","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585456","url":null,"abstract":"Using the model developed by Mead and Conway for charge based technology, a methodology for the production of area-time efficient adders which imbeds the buffering required to drive large loads caused by the carry-lookahead tree has been developed. This methodology can be used to produce an 0(logN) time and 0(NlogN) area layout. Additionally, an algorithm was written to produce minimal silicon area layouts for a given time bound. This algorithm involves optimization at both the cellular level and the layout level in an iterative fashion to allow the relevant technological parameters to play a role in the cellular design phase. Results of the algorithm including examples and an area-time curve for a 48 bit adder using typical 5 micron NMOS [MeCo80] are displayed.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122035222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信