A Low Cost Hierarchical System for VLSI Layout and Verification

Abstract

With IC complexity and the manhour effort required for design doubling every two years, new approaches to layout and mask verification are required. A low-cost VLSI layout and verification system was developed to produce cost effective designs using present resources. The system is IC technology independent, makes effective use of present design skills while maintaining density, and includes structured and behavioral intelligence to aid design verification. In addition, it is easy to learn to use since it provides a simplified design methodology for layout.