门阵列母片集成计算机辅助设计系统:第二部分Mars-M3布局设计系统

18th Design Automation Conference Pub Date : 1981-06-29 DOI:10.1109/DAC.1981.1585450

C. Tanaka, S. Murai, Hiroo Tsuji, T. Yahara, K. Okazaki, M. Terai, R. Katoh, Mikio Tachibana

{"title":"门阵列母片集成计算机辅助设计系统:第二部分Mars-M3布局设计系统","authors":"C. Tanaka, S. Murai, Hiroo Tsuji, T. Yahara, K. Okazaki, M. Terai, R. Katoh, Mikio Tachibana","doi":"10.1109/DAC.1981.1585450","DOIUrl":null,"url":null,"abstract":"Described are the outline and the application results of a fully automatic chip layout design system which has been utilized for years for the development of over a hundred options of ECL and MOS gate arrays. The features and techniques of the placement, routing and checking subsystems as well as the chip layout model which can be treated by the system are discussed.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"An Integrated Computer Aided Design System for Gate Array Masterslices: Part 2 The Layout Design System Mars-M3\",\"authors\":\"C. Tanaka, S. Murai, Hiroo Tsuji, T. Yahara, K. Okazaki, M. Terai, R. Katoh, Mikio Tachibana\",\"doi\":\"10.1109/DAC.1981.1585450\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Described are the outline and the application results of a fully automatic chip layout design system which has been utilized for years for the development of over a hundred options of ECL and MOS gate arrays. The features and techniques of the placement, routing and checking subsystems as well as the chip layout model which can be treated by the system are discussed.\",\"PeriodicalId\":201443,\"journal\":{\"name\":\"18th Design Automation Conference\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1981-06-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"18th Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1981.1585450\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"18th Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1981.1585450","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 11

摘要

介绍了一种全自动芯片布局设计系统的概要和应用结果，该系统已用于开发一百多种ECL和MOS门阵列。讨论了该系统可处理的布局、布线和检测子系统的特点和技术，以及芯片布局模型。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An Integrated Computer Aided Design System for Gate Array Masterslices: Part 2 The Layout Design System Mars-M3

Described are the outline and the application results of a fully automatic chip layout design system which has been utilized for years for the development of over a hundred options of ECL and MOS gate arrays. The features and techniques of the placement, routing and checking subsystems as well as the chip layout model which can be treated by the system are discussed.

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18th Design Automation Conference

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