A MOS/LSI Oriented Logic Simulator

Abstract

A logic simulator capable of efficiently modelling complex MOS/LSI circuits is presented. The circuit is simulated at the combinational logic and transmission gate level using a set of six node-states. Gate models have inertial delay and assignable nominal rise and fall delays. Both unidirectional and bidirectional transmission gates are accurately simulated, and functional models are provided for ROM, RAM, etc.