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CELTIC - Solving the Problems of LSI Design with an Integrated Polycell DA System 用集成多单元DA系统解决LSI设计问题
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585449
G. Martin, J. Berrie, T. Little, D. Mackay, J. McVean, D. Tomsett, L. Weston
{"title":"CELTIC - Solving the Problems of LSI Design with an Integrated Polycell DA System","authors":"G. Martin, J. Berrie, T. Little, D. Mackay, J. McVean, D. Tomsett, L. Weston","doi":"10.1109/DAC.1981.1585449","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585449","url":null,"abstract":"The major problems associated with LSI design include those of design complexity, documentation, mapping, design verification both functional and physical, physical implementation, and the manufacturing interface. The Design Aids group at Burroughs, Cumbernauld, have developed an integrated LSI design system, CELTIC, which solves these problems with a polycell design approach, direct graphics entry of logic diagrams, and automatic generation of LSI layouts. The system reduces the time required to lay out LSI's from months to weeks.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127132229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Hughes Automated Layout System - Automated LSI/VLSI Layout Based on Channel Routing 休斯自动布局系统-基于通道路由的自动LSI/VLSI布局
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585327
G. Persky, C. Enger, Matthew Selove
{"title":"The Hughes Automated Layout System - Automated LSI/VLSI Layout Based on Channel Routing","authors":"G. Persky, C. Enger, Matthew Selove","doi":"10.1109/DAC.1981.1585327","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585327","url":null,"abstract":"The Hughes Automated Layout System (HAL) is intended to provide fast, accurate, and efficient layout of LSI/VLSI circuits. The HAL development plan calls for an evolutionary development in three phases, with each phase providing a usable design system. HAL(I) is limited to standard cell layout and is now operational. HAL(II), which will permit more complex geometries, and HAL(III), which will add hierarchical capabilities, are in initial development. This paper discusses the features of HAL(I), and the concepts of decomposition and ordering of routing domains that underlie the more advanced systems.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115951600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An O (N log N) Algorithm for Boolean Mask Operations 一个O (N log N)的布尔掩码运算算法
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1145/62882.62909
U. Lauther
{"title":"An O (N log N) Algorithm for Boolean Mask Operations","authors":"U. Lauther","doi":"10.1145/62882.62909","DOIUrl":"https://doi.org/10.1145/62882.62909","url":null,"abstract":"A new algorithm is presented which calculates Boolean combinations (AND, OR, EXOR, AND NOT) between two layers of an integrated circuit layout. Input and output of the algorithm is an edgebased description of the set of polygons which represent the artwork. The algorithm has O (N log N) time and PI Left column, top. space complexity, i.e. it is faster than previously published methods. Moreover, we believe that it is easier to understand and to implement than the previously leading method in the field.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"46 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114017431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 80
GSP: A Logic Simulator for LSI 用于大规模集成电路的逻辑模拟器
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585405
J. Armstrong, D. E. Devlin
{"title":"GSP: A Logic Simulator for LSI","authors":"J. Armstrong, D. E. Devlin","doi":"10.1109/DAC.1981.1585405","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585405","url":null,"abstract":"A general simulation program for LSI devices is described. The program provides functional simulation capability as well as the ability to simulate chip interface timing. Chip modeling utilizes chip input/output specifications and timing diagrams. Construction and coding of the model is a process very much akin to assembly language programming. GSP is a program suitable for the simulation of LSI devices as it allows for a manageable amount of detail in model descriptions and can simulate with an efficiency that is adequate for system validation activities.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121269215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Placement of Variable Size Circuits on LSI Masterslices 可变尺寸电路在LSI母片上的放置
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585391
K. H. Khokhani, Arvind M. Patel, W. Ferguson, J. Sessa, D. Hatton
{"title":"Placement of Variable Size Circuits on LSI Masterslices","authors":"K. H. Khokhani, Arvind M. Patel, W. Ferguson, J. Sessa, D. Hatton","doi":"10.1109/DAC.1981.1585391","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585391","url":null,"abstract":"With the advent of large scale integration (LSI and VLSI), logic circuit densities per chip have grown to hundreds and thousands. The arrangement of interconnected logic circuits of different sizes and shapes poses a difficult combinatorial placement problem. In this paper, an overview of techniques is presented for placing different size rectangular circuits with limited locations on the chip, considering the function of level sensitive scan design (LSSD) [1], as well as wirability and electrical constraints. The automatic placement program (APLACE), encompassing techniques to handle various constraints, was developed in IBM's Engineering Design System. An overview is presented of the technique for partitioning logic into clusters (supernodes) and breaking the image down into a rectangular grid (super locations) for initial placement. [2] Iterative techniques that improve the initial placement and satisfy wirability and electrical (D.C. and capacitance) constraints are outlined. The concepts of zero ground interchange to balance horizontal and vertical channel demand and zonal movement to distribute wiring are presented. APLACE was developed primarily for the layout of the 704 gate masterslice used extensively in IBM's System 3081, encompassing 750,000 circuits. It has been in extensive use in IBM since the early 1970's to design thousands of masterslice chips ranging from 320-1500 circuits for IBM's System 38, [3][4] System 4341, [5] System 8100, for the 5000 gate array microprocessor [6][7] and for many others. The automatic layout method, APLACE, reduces design cycle time considerably and requires little or no manual intervention.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132679465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Automatic Component Placement in an Interactive Minicomputer Environment 交互式微型计算机环境中的自动组件放置
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585345
Charles F. Shupe
{"title":"Automatic Component Placement in an Interactive Minicomputer Environment","authors":"Charles F. Shupe","doi":"10.1109/DAC.1981.1585345","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585345","url":null,"abstract":"A minicomputer-based, second-generation automatic component placement facility has been implemented in the NOMAD System. Features include a new connectivity algorithm and an advanced algorithm for non-modular (no-site) placement.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114218717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Automatic PLA Synthesis from a DDL-P Description 从DDL-P描述自动PLA合成
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585386
Sungho Kang, W. M. V. Cleemput
{"title":"Automatic PLA Synthesis from a DDL-P Description","authors":"Sungho Kang, W. M. V. Cleemput","doi":"10.1109/DAC.1981.1585386","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585386","url":null,"abstract":"This paper describes an automatic PLA synthesis (APLAS) system which automatically generates a PLA for the control function of a design from a DDL-P description of a digital system. APLAS can also minimize and partition the PLA to meet the design constraints. This is a very convenient tool for designing finite state machines. The control circuit of any digital system for which a state diagram can be drawn can be designed easily using this system.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130905086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Process Oriented Logic Simulation 面向过程的逻辑仿真
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585404
Sany M. Leinwand
{"title":"Process Oriented Logic Simulation","authors":"Sany M. Leinwand","doi":"10.1109/DAC.1981.1585404","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585404","url":null,"abstract":"Theoretically, simulation can be activity oriented, event oriented or process oriented. Existing techniques for logic simulation are either activity or event oriented. In this paper, the possibility of logic simulation using process oriented concepts is investigated. Such an approach is justified by the need to support modular design environments. The key feature is that of asynchronous module activity: the timing order of signal changes has to be preserved only for those events belonging to the same module. It is shown that as long as the proper order of occurence for intermodule signaling is faithfully preserved, a centralized scheduling of events is avoidable. Thus, sequences of uninterruptible local events (termed atomic activities) can be simulated in complete isolation. The correct definition of uninterruptible local activities needs some information on allowable timing of interface events.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122431631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Creating and Updating Space Occupancy and Building Plans using Interactive Graphics 使用交互式图形创建和更新空间占用和建筑计划
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585333
R. Scoble
{"title":"Creating and Updating Space Occupancy and Building Plans using Interactive Graphics","authors":"R. Scoble","doi":"10.1109/DAC.1981.1585333","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585333","url":null,"abstract":"Interactive graphics systems have been used for generating integrated circuit and printed circuit layouts. Now these systems are being used to create building plans as well. This paper discusses the mechanization of \"rent plans\" (a set of plans which shows how building space is occupied), its background, several applications, and possible future developments.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"77 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120868762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The "Gap" Between Users and Designers of CAD/CAM Systems: Search for Solutions CAD/CAM系统的用户和设计者之间的“差距”:寻找解决方案
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585431
Joseph Peled, M. P. Carroll
{"title":"The \"Gap\" Between Users and Designers of CAD/CAM Systems: Search for Solutions","authors":"Joseph Peled, M. P. Carroll","doi":"10.1109/DAC.1981.1585431","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585431","url":null,"abstract":"The issue of the existing \"gap\" between users and developers of CAD/CAM systems was brought up at the panel discussion of last year's conference (17th DAC). The statements expressed were those of the users of CAD/CAM systems. This paper tries to bring the developer's viewpoint on this subject and suggestions for solving this problem, which is also the interest of the developers as well as the interest of the users of CAD/CAM systems.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122347240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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