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18th Design Automation Conference最新文献

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Diagnostic System for Large Scale Logic Cards and LSI'S 用于大型逻辑卡和LSI的诊断系统
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585360
Susumu Goshima, Yuichi Oka, T. Kozawa, Teruo Mori, Yoshimitsu Takeguchi, Yasuhiro Ohno
{"title":"Diagnostic System for Large Scale Logic Cards and LSI'S","authors":"Susumu Goshima, Yuichi Oka, T. Kozawa, Teruo Mori, Yoshimitsu Takeguchi, Yasuhiro Ohno","doi":"10.1109/DAC.1981.1585360","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585360","url":null,"abstract":"We have developed the diagnostic system, consisting of highly automated test generator, fast fault simulator and automatic fault locator. Several techniques, employed in the system, are as follows: 9-value D-Algorithm for sequential circuits., 6-value concurrent fault simulator., Functional Modeling of RAM'S, ROM'S, counters, and etc., Iterative processing of generator and simulator. This system has contributed to testing cards, and LSI'S used in Hitachi computer M-200H and others.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"02 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127166149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An Algorithm for Searching Shortest Path by Propagating Wave Fronts in Four Quadrants 基于四象限波前传播的最短路径搜索算法
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585328
Xiong Ji-Guang, T. Kozawa
{"title":"An Algorithm for Searching Shortest Path by Propagating Wave Fronts in Four Quadrants","authors":"Xiong Ji-Guang, T. Kozawa","doi":"10.1109/DAC.1981.1585328","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585328","url":null,"abstract":"This paper discusses a new algorithm for searching the shortest path in VLSIs by propagating wave fronts in four quadrants. The algorithm has been experimentally programmed in FORTRAN IV on a Hitac M-200H computer. The main advantages of this algorithm are: 1. When there is a shortest path between two points, it can always be found by this algorithm; 2. In this algorithm, searching waves are divided into four quadrants. In each quadrant, waves advance or trace-back independently, according to their own rules. Therefore, in the algorithm only the current waves and the next set of waves need to be remembered, irrespective of their history. Thus much less memory (about 1/10~1/100) is required than for Lee's algorithm [1] 3. During searching for a shortest path in this algorithm, only segments currently defined need to be investigated. This greatly cuts down operation time, when compared to for Lee's algorithm; 4. This algorithm may be more advisable than Lee's algorithm for application to multi-layer wiring.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126409257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A High-Density Multilayer PCB Router Based on Necessary and Sufficient Conditions for Single Row Routing 基于单行布线充分必要条件的高密度多层PCB路由器
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585384
R. Tsui, Robert J. Smith
{"title":"A High-Density Multilayer PCB Router Based on Necessary and Sufficient Conditions for Single Row Routing","authors":"R. Tsui, Robert J. Smith","doi":"10.1109/DAC.1981.1585384","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585384","url":null,"abstract":"This paper presents the necessary and sufficient conditions for routability of a list of two-point nets to be wired in a single row without using vias (single row routing) in a different formulation from that in [9]. These conditions are expressed in terms of left and right block counts (number of left and right blockages that will be encountered by each net if all nets in the list are routed in the same channel) of nets in the net list. An efficient routing algorithm which exploits these necessary and sufficient conditions is presented. Experimental results demonstrating the effectiveness of this algorithm are also given. Possible practical applications exploiting this set of necessary and sufficient conditions are suggested.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126531823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The Analog Behavior of Digital Integrated Circuits
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585416
L. Glasser
{"title":"The Analog Behavior of Digital Integrated Circuits","authors":"L. Glasser","doi":"10.1109/DAC.1981.1585416","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585416","url":null,"abstract":"The analog behavior of digital VLSI circuits is investigated. A theory based on nonlinear Thevenin equivalent circuits and RC ladder networks is developed. We obtain closed from expressions for the upper and lower bounds on propagation delay through a string of inverters. We generalize this to multiple-input, multiple-output gates and show that the problem of estimating signal propagation delays in VLSI circuits may be reduced to the problem of summing the step responses of a set of linear RC networks. As well as having implications for a computationally efficient timing simulator, the theory begins the formalization of the fundamental properties of digital integrated circuits.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127826251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Computer-Aided Design, Manufacturing, Assembly and Test (CADMAT) 计算机辅助设计、制造、装配和测试(CADMAT)
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585457
F. Bergsten
{"title":"Computer-Aided Design, Manufacturing, Assembly and Test (CADMAT)","authors":"F. Bergsten","doi":"10.1109/DAC.1981.1585457","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585457","url":null,"abstract":"This paper describes an integrated Computer-Aided Design, Manufacturing, Assembly and Test System to achieve increased productivity and quality. The term CADMAT which encompasses Automated Test also implies the integration of all design automated and computer augmented processes throughout the product and business organizations. In the design and test phase of electronics, Interactive Graphics (IAG), verification, automated board layout, and automatic test vector generation are discussed. In the mechanical area, the use of 2D and 3D graphics techniques, computerized finite element modeling, and structural analysis programs are described. The use of the design data base in N/C manufacturing, automated inspection and testing is examined as is the role of automated software development and the development and use of management information systems.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128770337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Symbolic Simulation for Functional Verification with ADLIB and SDL 用ADLIB和SDL进行功能验证的符号仿真
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585336
W. E. Cory
{"title":"Symbolic Simulation for Functional Verification with ADLIB and SDL","authors":"W. E. Cory","doi":"10.1109/DAC.1981.1585336","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585336","url":null,"abstract":"The basic verification problem addressed in this paper is to determine the consistency of two digital design descriptions. This is done by symbolically simulating each description and comparing the results. This approach is complicated by the presence of different levels of abstraction and asynchronous timing. This paper motivates interest in this problem and provides background information on verification, ADLIB, and SDL. It then discusses approaches for dealing with the problems encountered in the symbolic simulation of ADLIB/SDL descriptions.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131059602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
The Modeling and Synthesis of Bus Systems 公交系统的建模与综合
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585398
C. Tseng, D. Siewiorek
{"title":"The Modeling and Synthesis of Bus Systems","authors":"C. Tseng, D. Siewiorek","doi":"10.1109/DAC.1981.1585398","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585398","url":null,"abstract":"A bus oriented interconnection of registers and data operators is the dominant mode of design for the data paths of digital systems. A study of ten processor implementations, ranging in size from microprocessors to large mainframes, spanning almost 20 years in the practice of digital design, indicated a strong similarity. From this study bus style primitives and generic bus models were developed. The generic bus models were simplified to match each of the ten processors composing the study. An algorithm for generating a bus style design is presented. The algorithm is used to generate the data paths of the PDP-11/40 resulting in lower cost and shorter delays than the original implementation. Finally, the paper concludes with a discussion of the bus synthesis algorithm's implementation and its role in the CMU functional-to-hardware Design Automation System.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124087840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
SHARPS: A Hierarchical Layout System for VLSI SHARPS:一种用于VLSI的分层布局系统
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585451
T. Chiba, N. Okuda, T. Kambe, I. Nishioka, T. Inufushi, Sieji Kimura
{"title":"SHARPS: A Hierarchical Layout System for VLSI","authors":"T. Chiba, N. Okuda, T. Kambe, I. Nishioka, T. Inufushi, Sieji Kimura","doi":"10.1109/DAC.1981.1585451","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585451","url":null,"abstract":"A hierarchical layout system for VLSI provided with placement and routing facilities is described, highlighting the routing scheme constructed on the basis of a channel router. Several implementation results are also shown to reveal how much the system has potentialities to be of great use in the practice of layout design of full custom LSI's.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115812749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
An Algorithmic Pretest Development for Fault Identification in Analog Networks 模拟网络故障识别的预测试算法研究
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585353
V. Masurkar
{"title":"An Algorithmic Pretest Development for Fault Identification in Analog Networks","authors":"V. Masurkar","doi":"10.1109/DAC.1981.1585353","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585353","url":null,"abstract":"This paper describes the design and development of an algorithm for fault identification in electrical analog networks. The emphasis is on mathematical formulation of the problem and generation of a viable fault identification criterion. The method serves as a pretest for a catastrophic (or considerably out-of-tolerance) fault condition. Under non-accessibility of some of the nodes, the method estimates nodal voltages to arrive at an estimated admittance matrix for the faulty Unit Under Test (UUT). The simulation of networks is done through Electronic Circuit Analysis Program (ECAP).","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126192941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CAD for Military Systems, An Essential Link to LSI, VLSI and VHSIC Technology 军事系统CAD:集成电路、超大规模集成电路和超大规模集成电路技术的必要环节
18th Design Automation Conference Pub Date : 1981-06-29 DOI: 10.1109/DAC.1981.1585325
R. Reitmeyer
{"title":"CAD for Military Systems, An Essential Link to LSI, VLSI and VHSIC Technology","authors":"R. Reitmeyer","doi":"10.1109/DAC.1981.1585325","DOIUrl":"https://doi.org/10.1109/DAC.1981.1585325","url":null,"abstract":"Government involvement in the development of computer aided design (CAD) tools for electronic circuits has a long history. The advent of large scale integrated (LSI) circuits, going into the 1970's, pulsed the development of the \"standard cell\" and \"gate array\" design methodologies and supporting CAD. Despite these burgeoning technologies, little custom LSI technology found its way into military systems. Custom LSI was considered too costly and risky. Moving into the 1980's we find a vastly different Picture. DoD is closing the gap between fielded equipment and the use of advanced IC technology through the VHSIC and other VLSI technology insertion programs. The significance of this, is that CAD has become a critical technology and, as a result, is receiving considerable government funding.","PeriodicalId":201443,"journal":{"name":"18th Design Automation Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1981-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121016266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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