An Algorithmic Pretest Development for Fault Identification in Analog Networks

Abstract

This paper describes the design and development of an algorithm for fault identification in electrical analog networks. The emphasis is on mathematical formulation of the problem and generation of a viable fault identification criterion. The method serves as a pretest for a catastrophic (or considerably out-of-tolerance) fault condition. Under non-accessibility of some of the nodes, the method estimates nodal voltages to arrive at an estimated admittance matrix for the faulty Unit Under Test (UUT). The simulation of networks is done through Electronic Circuit Analysis Program (ECAP).