可变尺寸电路在LSI母片上的放置

K. H. Khokhani, Arvind M. Patel, W. Ferguson, J. Sessa, D. Hatton
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引用次数: 9

摘要

随着大规模集成电路(LSI和VLSI)的出现,每个芯片的逻辑电路密度已经增长到数百和数千。不同尺寸和形状的互连逻辑电路的排列构成了一个困难的组合布置问题。本文概述了在芯片上放置具有有限位置的不同尺寸矩形电路的技术,考虑到电平敏感扫描设计(LSSD)[1]的功能,以及连接性和电气约束。自动放置程序(APLACE)包含了处理各种约束的技术,是在IBM的工程设计系统中开发的。概述了将逻辑划分为集群(超级节点)和将图像分解为矩形网格(超级位置)以进行初始放置的技术。[2]迭代技术,改进初始布局和满足连接性和电气(直流和电容)的限制概述。提出了零地交换的概念,以平衡水平和垂直通道的需求和带状移动分布布线。APLACE主要是为IBM系统3081中广泛使用的704栅极母片的布局而开发的,包含750,000个电路。自20世纪70年代初以来,它已在IBM广泛使用,为IBM的System 38, [3][4] System 4341, [5] System 8100, 5000门阵列微处理器[6][7]和许多其他芯片设计了数千个从320-1500电路的主片芯片。自动布局方法,APLACE,大大缩短了设计周期时间,几乎不需要人工干预。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Placement of Variable Size Circuits on LSI Masterslices
With the advent of large scale integration (LSI and VLSI), logic circuit densities per chip have grown to hundreds and thousands. The arrangement of interconnected logic circuits of different sizes and shapes poses a difficult combinatorial placement problem. In this paper, an overview of techniques is presented for placing different size rectangular circuits with limited locations on the chip, considering the function of level sensitive scan design (LSSD) [1], as well as wirability and electrical constraints. The automatic placement program (APLACE), encompassing techniques to handle various constraints, was developed in IBM's Engineering Design System. An overview is presented of the technique for partitioning logic into clusters (supernodes) and breaking the image down into a rectangular grid (super locations) for initial placement. [2] Iterative techniques that improve the initial placement and satisfy wirability and electrical (D.C. and capacitance) constraints are outlined. The concepts of zero ground interchange to balance horizontal and vertical channel demand and zonal movement to distribute wiring are presented. APLACE was developed primarily for the layout of the 704 gate masterslice used extensively in IBM's System 3081, encompassing 750,000 circuits. It has been in extensive use in IBM since the early 1970's to design thousands of masterslice chips ranging from 320-1500 circuits for IBM's System 38, [3][4] System 4341, [5] System 8100, for the 5000 gate array microprocessor [6][7] and for many others. The automatic layout method, APLACE, reduces design cycle time considerably and requires little or no manual intervention.
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