2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)最新文献_第2页

Clock domain verification challenges and scalable solutions 时钟域验证挑战和可扩展的解决方案

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496661

P. Ashar

引用次数: 0

An ontology and constraint based approach to cache preloading 基于本体和约束的缓存预加载方法

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496651

Rajiv Bhatia, E. Bin, E. Marcus, G. Shurek

{"title":"An ontology and constraint based approach to cache preloading","authors":"Rajiv Bhatia, E. Bin, E. Marcus, G. Shurek","doi":"10.1109/HLDVT.2010.5496651","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496651","url":null,"abstract":"The verification of modern microprocessor-based systems requires stressing the cache hierarchy and effectively covering its huge state space. Cache hierarchy initialization (or preloading) is a technique that enables simulation to start from a rich, complex system-level setup, thereby simplifying the task of dynamically driving the hierarchy into the required corner cases. In this paper we introduce CacheLoader, a new, design-independent cache-preloading technology. The tool's architecture follows the principles of ontology-based software to achieve complete separation between the cache-preloading engine and design dependent knowledge. Constraint satisfaction techniques are used to generate valid, interesting system initialization, and to satisfy explicit user directives. CacheLoader is currently being used by verification teams of several large scale designs in IBM. Results show that this technique provides superior coverage and user controllability, speeds up the construction of mature verification environments, simplifies maintenance, encourages encapsulation of domain knowledge, and enables reuse across verification environments and cache hierarchy designs.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122005535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Utility of transaction-level hardware models in refinement checking 在精化检查中使用事务级硬件模型

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496650

Yogesh S. Mahajan, S. Malik

引用次数: 1

Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs OSCI TLM-2.0模型自动合成基于RTL总线的ip

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496652

N. Bombieri, F. Fummi, V. Guarnieri

{"title":"Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs","authors":"N. Bombieri, F. Fummi, V. Guarnieri","doi":"10.1109/HLDVT.2010.5496652","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496652","url":null,"abstract":"Transaction-level modeling (TLM) is the most promising technique to deal with the increasing complexity of modern embedded systems. TLM provides designers with high-level interfaces and communication protocols for abstract modeling and efficient simulation of system platforms. The Open SystemC Initiative (OSCI) has recently released the TLM-2.0 standard, to standardize the interface between component models for bus-based systems. The TLM standard aims at facilitating the interchange of models between suppliers and users, and thus encouraging the use of virtual platforms for fast simulation prior to the availability of register-transfer level (RTL) code. On the other hand, because a TLM IP description does not include the implementation details that must be added at the RTL, the process to synthesize TLM designs into RTL implementations is still manual, time spending and error prone. In this context, this paper presents a methodology for automating the TLM-to-RTL synthesis by applying the theory of high-level synthesis (HLS) to TLM, and proposes a protocol synthesis technique based on the extended finite state machine (EFSM) model for generating the RTL IP interface compliant with any RTL bus-based protocol.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128471650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks 带反馈的定点线性算术电路的量程和精度分析

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496667

O. Sarbishei, Yu Pang, K. Radecka

引用次数: 18

Semi-formal functional verification by EFSM traversing via NuSMV 通过NuSMV遍历EFSM的半形式化功能验证

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496660

G. D. Guglielmo, F. Fummi, G. Pravadelli, S. Soffia, Marco Roveri

{"title":"Semi-formal functional verification by EFSM traversing via NuSMV","authors":"G. D. Guglielmo, F. Fummi, G. Pravadelli, S. Soffia, Marco Roveri","doi":"10.1109/HLDVT.2010.5496660","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496660","url":null,"abstract":"Simulation-based verification of hardware systems is well-established in industrial practice thanks to the ease-of-use of the approach and to its scalability. However, it notoriously suffers from the lack of exhaustiveness. On the other hand, while pure formal verification techniques provide high confidence in the design correctness, they are very limited in terms of scalability. As an alternative, semi-formal validation techniques are currently under investigation. Semi-formal approaches fulfil the tradeoff between high-coverage results, scalability of the design, and reduced resource requirements. In this work, a semi-formal approach for hardware verification is presented by exploiting constrained random simulation and extended finite state machine (EFSM) traversal through heuristics. The proposed heuristics aim to uniformly, and rapidly, visit the design space, exploiting a NuSMV-based constraint solving technique to efficiently cover corner cases. In this context, a constraint solving interface has been built on top of the NuSMV model checker. We present experimental results comparing the proposed heuristics with existent approaches, and the effectiveness of our NuSMV-based strategy with respect to the adoption of a state of the art constraint solver (ECLiPSe).","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131764187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Model reduction techniques for the formal verification of hardware dependent software 硬件相关软件形式化验证的模型简化技术

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496647

W. Ecker, Volkan Esen, Rainer Findenig, T. Steininger, Michael Velten

引用次数: 4

Verification of real-time properties for Hardware-dependent Software 硬件相关软件的实时性验证

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496644

W. Mueller, Marcio Ferreira da Silva Oliveira, H. Zabel, Markus Becker

引用次数: 7

Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams 使用定时泰勒展开图重新计时算术数据路径

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496664

D. Gomez-Prado, Dusung Kim, M. Ciesielski, E. Boutillon

引用次数: 1

Towards analyzing functional coverage in SystemC TLM property checking SystemC TLM属性检查中的功能覆盖分析

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496658

H. M. Le, Daniel Große, R. Drechsler

{"title":"Towards analyzing functional coverage in SystemC TLM property checking","authors":"H. M. Le, Daniel Große, R. Drechsler","doi":"10.1109/HLDVT.2010.5496658","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496658","url":null,"abstract":"For Electronic System Level (ESL) design SystemC has become the standard language due to its excellent support of Transaction Level Modeling (TLM). But even if the complexity of the systems can be handled using the abstraction levels offered by TLM - the most abstract one is untimed and focuses on functionality - still verification is the major bottleneck. In particular, as untimed TLM models are the reference for the following refinement steps their correctness has to be ensured. Thus, formal verification approaches have been developed to prove properties for these models. However, even if several properties have been checked this does not guarantee that the complete functionality of the TLM model has been verified. Thus, in this paper we consider the problem of functional coverage analysis in formal TLM property checking. We present a coverage approach which can analyze whether the property set unambiguously describes all transactions in a SystemC TLM model. The developed coverage analysis method identifies uncovered scenarios and hence allows to close all coverage gaps. As an example we consider an automated teller machine and we show the benefits of the proposed approach.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121676630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16