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2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)最新文献

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An improvement in decomposed reachability analysis for symbolic model checking 符号模型检验中分解可达性分析的改进
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496663
Nicholas Donataccio, Hao Zheng
{"title":"An improvement in decomposed reachability analysis for symbolic model checking","authors":"Nicholas Donataccio, Hao Zheng","doi":"10.1109/HLDVT.2010.5496663","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496663","url":null,"abstract":"Even though BDD-based reachability analysis can handle many large designs, the BDD sizes still often explode, and its performance is hard to predict. To address this problem, several decomposed approaches are presented in [6] to perform approximate state space traversal on a partitioned design. These approaches use reachable states as invariants to constrain the inputs of each partition to reduce unreachable states. This paper presents an improvement such that the input behavior of each partition is constrained by the state transitions allowed by the source partitions where the inputs are defined. Experimental results show that this type of input constraints helps to produce tighter state space for each partition. Furthermore, the effect of design partitioning on the performance is also discussed.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123180519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A case study of Time-Multiplexed Assertion Checking for post-silicon debugging 时间复用断言检查在硅后调试中的应用研究
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496657
Ming Gao, K. Cheng
{"title":"A case study of Time-Multiplexed Assertion Checking for post-silicon debugging","authors":"Ming Gao, K. Cheng","doi":"10.1109/HLDVT.2010.5496657","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496657","url":null,"abstract":"Post-silicon debugging has become the least predictable and most labor-intensive step in the modern design flow at 65nm and below. In this paper, we present a design-for-debug (DfD) technique - named Time-Multiplexed Assertion Checking (TMAC) - for post-silicon bug detection and isolation. By instantiating assertion checkers in an on-chip reconfigurable block (either an embedded FPGA block or a spare programmable core) in a time-multiplexed fashion, TMAC enables hardware implementation of a large number of assertion checkers on-chip with a trivial area overhead. In a case study of an H.264 decoder, a TMAC implementation with eighty time-multiplexed assertion checkers are compared with an ASIC implementation with and without dedicated assertion checkers. Experimental results demonstrate that, among those injected bugs that cannot be detected by a comprehensive set of testbenches for the decoder, those eighty hardware assertion checkers can successfully detect 39.4% of these hard-to-detect bugs. With TMAC, the area overhead is only 1.3%. Moreover, TMAC significantly reduces the time and effort for identifying the root causes of these detected bugs. The case study shows that, on average, the TMAC checkers reduces the bug detection latency by 87 times, and the location of the first assertion violation can help quickly localize the faulty design module.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129014048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
ESL flows are enabled by high-level synthesis with universality ESL流是通过具有普遍性的高级综合实现的
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496648
R. Nikhil
{"title":"ESL flows are enabled by high-level synthesis with universality","authors":"R. Nikhil","doi":"10.1109/HLDVT.2010.5496648","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496648","url":null,"abstract":"Due to their size and complexity, SoCs today require a “whole-system” approach to validation and verification, using real data traffic, throughout the design cycle. Instead of isolated IP verification with custom testbenches, followed by system integration, designers need to start with whole-system models in which subsystems can be independently substituted by refined models and IP blocks, so that there is a continuous system-level validation. Design languages need to be universal to express configurations that are so heterogeneous, both in the functionality and in level of abstraction. Further, they need to be universally synthesizable so that any such configuration can be run on hardware-assisted verification platforms (such as FPGAs) to achieve the speeds needed for meaningful validation and verification.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114932306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The relationship of code coverage metrics on high-level and RTL code 高级代码和RTL代码上的代码覆盖度量的关系
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496649
J. Sanguinetti, E. Zhang
{"title":"The relationship of code coverage metrics on high-level and RTL code","authors":"J. Sanguinetti, E. Zhang","doi":"10.1109/HLDVT.2010.5496649","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496649","url":null,"abstract":"Code coverage is a standard tool for obtaining an indication of the quality of testing done for a hardware design. This is generally applied to the RTL code for a design. As hardware design is moving to a higher level, it is desirable to apply such tools to the original design source code. The high-level code is synthesized into RTL, which is the traditional design representation to which code coverage is applied. It would be desirable to know how code coverage at the higher level is correlated to code coverage at the RTL. However, line coverage, which is commonly used for high-level code, is known to have little correlation to coverage metrics obtained from the RTL produced from the high-level code. In this exercise, we obtain coverage metrics from a high-level model, produce RTL from it using a high-level synthesis tool, and compare those results with RTL coverage metrics. The correlation obtained for this example is quite good.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122336418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Fast and accurate UML State Chart modeling using TLM+ control flow abstraction 使用TLM+控制流抽象快速准确的UML状态图建模
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496654
Rainer Findenig, T. Leitner, Michael Velten, W. Ecker
{"title":"Fast and accurate UML State Chart modeling using TLM+ control flow abstraction","authors":"Rainer Findenig, T. Leitner, Michael Velten, W. Ecker","doi":"10.1109/HLDVT.2010.5496654","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496654","url":null,"abstract":"The execution speed of classical HW-centric State Charts can be improved by at least one magnitude when migrating from a clock based execution to a transaction event based execution. Applying control flow abstraction, e.g. migrating from transaction event triggers to block transfer triggers, gives a further improvement in execution speed. Timing accuracy is preserved by separation of time and control using a resource model. The paper presents the methodology of control flow abstraction and the implementation consisting of code generation from UML, the resource model control interfaces, and the resource model implementation. An industrial example concludes the paper.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123194841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks 获得一致的全局状态转储，以便在具有多个时钟的芯片上交互式调试系统
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496668
B. Vermeulen, K. Goossens
{"title":"Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks","authors":"B. Vermeulen, K. Goossens","doi":"10.1109/HLDVT.2010.5496668","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496668","url":null,"abstract":"Post-silicon debugging of a system on chip (SOC) is complex due to (1) the intrinsic limits on the internal observability, (2) the absence of a single global clock, and (3) the need for asynchronous intellectual property (IP) blocks to interact with each other. These aspects prevent the instantaneous capture of a complete and consistent state of the SOC, and make the SOC non-deterministic at both the clock cycle level and the behavioral level. To debug an embedded system when the states that are extracted are irreproducible and inconsistent is nearly impossible. In this paper, we therefore introduce a method to capture a consistent, complete state of a multiple-clock SOC for interactive debugging. We reuse the same functionality that is used to ensure correct functional communication between asynchronous IP blocks, namely the handshake signals common in on-chip communication protocols. We merge the required on-chip hardware to support this debug functionality with the traditional debug architecture that reuses the manufacturing scan chains for debug. Our experimental results show that it is possible to ensure a globally consistent state is observed when the system is stopped on a breakpoint event.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126808715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Quick formal modeling of communication fabrics to enable verification 通信结构的快速形式化建模以支持验证
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496662
S. Chatterjee, M. Kishinevsky, Ümit Y. Ogras
{"title":"Quick formal modeling of communication fabrics to enable verification","authors":"S. Chatterjee, M. Kishinevsky, Ümit Y. Ogras","doi":"10.1109/HLDVT.2010.5496662","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496662","url":null,"abstract":"Although communication fabrics at the microarchitectural level are mainly composed of standard primitives such as queues and arbiters, to get an executable model one has to connect these primitives with glue logic to complete the description. In this paper we identify a richer set of microarchitectural primitives that allows us to describe complete systems by composition alone. This enables us to build models faster (since models are now simply wiring diagrams at an appropriate level of abstraction) and to avoid common modeling errors such as inadvertent loss of data due to incorrect timing assumptions. Our models are formal and they are used for model checking as well as dynamic validation and performance modeling. However, unlike other formalisms this approach leads to a precise yet intuitive graphical notation for microarchitecture that captures timing and functionality in sufficient detail to be useful for reasoning about correctness and for communicating microarchitectural ideas to RTL and circuit designers and validators.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116695389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Automatic generation of host-compiled timed TLMs for high level design 为高级设计自动生成主机编译的定时tlm
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496655
S. Abdi
{"title":"Automatic generation of host-compiled timed TLMs for high level design","authors":"S. Abdi","doi":"10.1109/HLDVT.2010.5496655","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496655","url":null,"abstract":"This paper presents a case for using automatically generated transaction level models (TLMs) for high level design. The inputs to automatic TLM generation are application C tasks mapped to processing units in the platform. Based on the mapping, the basic blocks in the C tasks are analyzed and annotated with estimated delays. The delay-annotated C code is linked with a SystemC model of the platform's communication architecture to generate the TLM. The TLM is compiled and executed natively on the host machine, making it much faster than conventional cycle accurate models. TLMs for industrial scale designs such as MP3 decoder have been shown to simulate in seconds, compared to 3–4 hrs of instruction set simulation (ISS) and 15–18 hrs of RTL simulation. Timing estimation error over board simulation has been shown to be less than 15%.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121759438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Static analysis of deadends in SVA constraints SVA约束下死角的静力分析
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496656
Ashvin Dsouza
{"title":"Static analysis of deadends in SVA constraints","authors":"Ashvin Dsouza","doi":"10.1109/HLDVT.2010.5496656","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496656","url":null,"abstract":"When sequential constraints are used in constrained random simulation, it is possible for the choice of solution for the constraints at any cycle to lead to a deadend at a later cycle. A deadend occurs when the constraints have no solution, which indicates a problem with the constraints. We describe a method to identify deadends for a set of SVA constraints and to generate additional SVA constraints that will prevent these deadends. The generated constraints provide insight into the nature of the deadends and help to resolve them. Our method for identifying deadends also makes use of an efficient technique for finding minimal unsatisfiable subsets of an unsatisfiable set of Boolean expressions.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"2418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130755870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
State space reductions for scalable verification of asynchronous designs 异步设计的可扩展验证的状态空间缩减
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496666
Haiqiong Yao, Hao Zheng, C. Myers
{"title":"State space reductions for scalable verification of asynchronous designs","authors":"Haiqiong Yao, Hao Zheng, C. Myers","doi":"10.1109/HLDVT.2010.5496666","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496666","url":null,"abstract":"This paper presents several state space reductions for verifying non-trivial asynchronous designs with a compositional minimization approach. These reductions result in a reduced model that contains the exact set of observably equivalent behavior. Therefore no false counter-examples are produced at the end of verification. The experimental results show good scale-up of compositional minimization using these reductions on a number of asynchronous designs.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129458651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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