{"title":"异步设计的可扩展验证的状态空间缩减","authors":"Haiqiong Yao, Hao Zheng, C. Myers","doi":"10.1109/HLDVT.2010.5496666","DOIUrl":null,"url":null,"abstract":"This paper presents several state space reductions for verifying non-trivial asynchronous designs with a compositional minimization approach. These reductions result in a reduced model that contains the exact set of observably equivalent behavior. Therefore no false counter-examples are produced at the end of verification. The experimental results show good scale-up of compositional minimization using these reductions on a number of asynchronous designs.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"State space reductions for scalable verification of asynchronous designs\",\"authors\":\"Haiqiong Yao, Hao Zheng, C. Myers\",\"doi\":\"10.1109/HLDVT.2010.5496666\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents several state space reductions for verifying non-trivial asynchronous designs with a compositional minimization approach. These reductions result in a reduced model that contains the exact set of observably equivalent behavior. Therefore no false counter-examples are produced at the end of verification. The experimental results show good scale-up of compositional minimization using these reductions on a number of asynchronous designs.\",\"PeriodicalId\":200068,\"journal\":{\"name\":\"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HLDVT.2010.5496666\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HLDVT.2010.5496666","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
State space reductions for scalable verification of asynchronous designs
This paper presents several state space reductions for verifying non-trivial asynchronous designs with a compositional minimization approach. These reductions result in a reduced model that contains the exact set of observably equivalent behavior. Therefore no false counter-examples are produced at the end of verification. The experimental results show good scale-up of compositional minimization using these reductions on a number of asynchronous designs.