A case study of Time-Multiplexed Assertion Checking for post-silicon debugging

Abstract

Post-silicon debugging has become the least predictable and most labor-intensive step in the modern design flow at 65nm and below. In this paper, we present a design-for-debug (DfD) technique - named Time-Multiplexed Assertion Checking (TMAC) - for post-silicon bug detection and isolation. By instantiating assertion checkers in an on-chip reconfigurable block (either an embedded FPGA block or a spare programmable core) in a time-multiplexed fashion, TMAC enables hardware implementation of a large number of assertion checkers on-chip with a trivial area overhead. In a case study of an H.264 decoder, a TMAC implementation with eighty time-multiplexed assertion checkers are compared with an ASIC implementation with and without dedicated assertion checkers. Experimental results demonstrate that, among those injected bugs that cannot be detected by a comprehensive set of testbenches for the decoder, those eighty hardware assertion checkers can successfully detect 39.4% of these hard-to-detect bugs. With TMAC, the area overhead is only 1.3%. Moreover, TMAC significantly reduces the time and effort for identifying the root causes of these detected bugs. The case study shows that, on average, the TMAC checkers reduces the bug detection latency by 87 times, and the location of the first assertion violation can help quickly localize the faulty design module.