2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)最新文献_第3页

Automated synthesis of EDACs for FLASH memories with user-selectable correction capability 自动合成EDACs的闪存与用户可选择的校正能力

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496653

M. Caramia, M. Fabiano, Andrea Miele, Roberto Piazza, P. Prinetto

{"title":"Automated synthesis of EDACs for FLASH memories with user-selectable correction capability","authors":"M. Caramia, M. Fabiano, Andrea Miele, Roberto Piazza, P. Prinetto","doi":"10.1109/HLDVT.2010.5496653","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496653","url":null,"abstract":"Tackling the design of a mission-critical system is a rather complex task: different and quite often contrasting dimensions need to be explored and the related trade-offs need to be evaluated. Designing a mass-memory device is one of the typical issues of mission-critical applications: the whole system is expected to accomplish a high level of dependability which highly relies on the dependability provided by the mass-memory device itself. NAND flash-memories could be used for this goal: in fact on the one hand they are nonvolatile, shock-resistant and powereconomic but on the other hand they have several drawbacks (e.g., higher cost and number of erasure cycles bounded). Error Detection And Correction (EDAC) techniques could be exploited to improve dependability of flash-memory devices: in particular binary Bose and Ray-Chaudhuri (BCH) codes are a well known correcting code technique for NAND flash-memories. In spite of the importance of error correction capability several other equally critical dimensions need to be explored during the design of binary BCH codes for a flashmemory based mass-memory device. No systematic approach has so far been proposed to consider them all as a whole: as a consequence a novel design environment with a user-selectable error correction capability is aimed at supporting the design of binary BCH codes for a flash-memory based mass-memory device.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125258660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

ESL design and multi-core validation using the System-on-Chip Environment 使用片上系统环境的ESL设计和多核验证

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496646

Weiwei Chen, Xu Han, R. Dömer

引用次数: 7

Coverage metrics for verification of concurrent SystemC designs using mutation testing 使用突变测试验证并发SystemC设计的覆盖度量

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-10 DOI: 10.1109/HLDVT.2010.5496659

A. Sen, M. Abadir

{"title":"Coverage metrics for verification of concurrent SystemC designs using mutation testing","authors":"A. Sen, M. Abadir","doi":"10.1109/HLDVT.2010.5496659","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496659","url":null,"abstract":"Design verification has grown to dominate the cost of electronic system design; however, designs continue to be released with latent bugs. A verification test suite developed for a sequential program is not adequate for a concurrent program. A major problem with design verification of concurrent systems is the lack of good coverage metrics. Coverage metrics are heuristic measures of the exhaustiveness of a test suite. High coverage, in general, implies fewer bugs. SystemC is the most popular concurrent system level modeling language used for designing SoCs in the industry. We propose to attack the verification quality problem for concurrent SystemC programs by developing novel mutation testing based coverage metrics. Mutation testing has successfully been applied in software testing and RTL designs. In this paper, we develop a comprehensive set of mutation operators for concurrency constructs in SystemC. Our approach is also unique in that we define a novel concurrent coverage metric considering multiple execution schedules that a concurrent program can generate. This metric allows us to adequately measure the coverage for concurrent programs. We performed experiments with various designs including a large industrial design and obtained favorable results on multiple applications.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127704322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

System level simulation guided approach to improve the efficacy of clock-gating 采用系统级仿真指导方法提高时钟门控的效率

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2010-06-01 DOI: 10.1109/HLDVT.2010.5496669

Sumit Ahuja, Wei Zhang, S. Shukla

{"title":"System level simulation guided approach to improve the efficacy of clock-gating","authors":"Sumit Ahuja, Wei Zhang, S. Shukla","doi":"10.1109/HLDVT.2010.5496669","DOIUrl":"https://doi.org/10.1109/HLDVT.2010.5496669","url":null,"abstract":"Clock-gating is a well known technique to reduce dynamic power consumption of a hardware design. In any clock-gating based power reduction flow, automatic selection of appropriate registers and/or register banks is extremely time-consuming because power analysis is performed at the RTL or lower level. In a high-level synthesis (HLS) based design flow, to achieve faster design closure, one must be able to decide the appropriate set of registers to clock gate even before generating RTL. System-level simulations are known to provide faster simulation, yet there is no solution, which utilizes systemlevel simulation to provide guidance to HLS to create clock-gated RTL. Since predicting power reduction at higher levels of abstraction is difficult due to the dependence of power on physical details, an accurate and efficient relative power reduction model is required. In this paper, we propose a novel system-level design methodology, which utilizes a ‘relative power reduction model’ that can help in predicting the impact of clock-gating on each register/bank quickly and accurately, by simulating the design at a cycle accurate transaction-level. As a result, our approach can automatically find the appropriate registers to clock-gate, guided by the system-level simulation.","PeriodicalId":200068,"journal":{"name":"2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126331706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5