Semi-formal functional verification by EFSM traversing via NuSMV

Abstract

Simulation-based verification of hardware systems is well-established in industrial practice thanks to the ease-of-use of the approach and to its scalability. However, it notoriously suffers from the lack of exhaustiveness. On the other hand, while pure formal verification techniques provide high confidence in the design correctness, they are very limited in terms of scalability. As an alternative, semi-formal validation techniques are currently under investigation. Semi-formal approaches fulfil the tradeoff between high-coverage results, scalability of the design, and reduced resource requirements. In this work, a semi-formal approach for hardware verification is presented by exploiting constrained random simulation and extended finite state machine (EFSM) traversal through heuristics. The proposed heuristics aim to uniformly, and rapidly, visit the design space, exploiting a NuSMV-based constraint solving technique to efficiently cover corner cases. In this context, a constraint solving interface has been built on top of the NuSMV model checker. We present experimental results comparing the proposed heuristics with existent approaches, and the effectiveness of our NuSMV-based strategy with respect to the adoption of a state of the art constraint solver (ECLiPSe).