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ESSCIRC '88: Fourteenth European Solid-State Circuits Conference最新文献

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A CMOS Bandgap Reference with Reduced Offset Sensitivity 降低偏置灵敏度的CMOS带隙基准
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468341
Eric Holle
{"title":"A CMOS Bandgap Reference with Reduced Offset Sensitivity","authors":"Eric Holle","doi":"10.1109/ESSCIRC.1988.5468341","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468341","url":null,"abstract":"A new circuit technique to realize a voltage reference in a CMOS process based on the bandgap reference principle is discussed. The reference voltage can be chosen freely as long as it is greater than or equal to the silicon bandgap voltage. The circuit combines a reduced sensitivity for MOS amplifier offset with a reduction of chip area occupied by resistors. The validity of the circuit technique has been demonstrated on silicon.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128380104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Smartpower Innovative Actuator in Automotive Field 智能动力汽车领域的创新执行器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468296
M. Zisa
{"title":"A Smartpower Innovative Actuator in Automotive Field","authors":"M. Zisa","doi":"10.1109/ESSCIRC.1988.5468296","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468296","url":null,"abstract":"This work describes a electronic device, made by a new smartpower technology: VIPower-M2/BCD. The component is a monolithic switch self protected, it is a high side driver which can drive inductive or resistive loads with a grounded terminal. The device merges on the same chip a Powermos transistor delivering up to 25.4 with 1.2V voltage drop and 0.04¿ of RDSON, with a logic and analog circuit in bipolar, CMOS, DMOS technology. It is protected against short circuit, over voltage, over temperature and has a diagnostic output which signals previous fault conditions and allows the communication between chip and outside world. The technology allows a supply voltage up to 60V and the implementation on one chip of functions before realized by two or more devices.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129331303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Low Noise CMOS Integrated Signal Processor for Multi-Element Particle Detectors 用于多元素粒子探测器的低噪声CMOS集成信号处理器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468440
E. Heijne, P. Jarron
{"title":"A Low Noise CMOS Integrated Signal Processor for Multi-Element Particle Detectors","authors":"E. Heijne, P. Jarron","doi":"10.1109/ESSCIRC.1988.5468440","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468440","url":null,"abstract":"A full custom chip has been built for readout of a multi-element silicon detector in the UA2 collider experiment at CERN. The low-noise performance enables the use of this chip for detecting random particles or single X-ray photons of medium energy (~ 20 keV). It can be used equally well in various other types of particle detectors which produce random signals. The noise is sufficiently low (≪ 0.09 fC r.m.s.) for detection of signals of ~ 0.8 fC, corresponding to 20 keV energy deposit in a silicon detector.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134442890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A Comparison of GaAs HJBT and Silicon Bipolar Technologies For High Speed Analogue to Digital Converters 用于高速模拟数字转换器的GaAs HJBT和硅双极技术的比较
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468275
A. Joy, A. Holden, T. Leslie, P. Saul
{"title":"A Comparison of GaAs HJBT and Silicon Bipolar Technologies For High Speed Analogue to Digital Converters","authors":"A. Joy, A. Holden, T. Leslie, P. Saul","doi":"10.1109/ESSCIRC.1988.5468275","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468275","url":null,"abstract":"The potential using the emerging GaAlAs/GaAs heterojunction bipolar transistor (HJBT) technology is all-parallel analog-to-digital (A/D) converters is studied. To put into perspective the HJBT predictions made, a comparison of the ultimate performance levels achievable with contemporary silicon bipolar processes is given. Optimized latched compensators were developed for each technology and simulations on SPICE were carried out to determine the maximum sample rate and large-signal analog bandwidths that would be achieved. As both technologies are produced in-house, models were available for processors in the latter stages of development, namely the standard 1- mu m silicon bipolar process, and the 4- mu m HJBT process, as well as processes at an earlier stage of development, the enhanced 1- mu m silicon bipolar processes and the 2.5- mu m HJBT process. This enabled the trend of performance improvements with time to be compared. >","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132041693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
CMOS Driver and Receiver Circuits for WSI Systems WSI系统的CMOS驱动和接收电路
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468361
G. Henning, K. Goser
{"title":"CMOS Driver and Receiver Circuits for WSI Systems","authors":"G. Henning, K. Goser","doi":"10.1109/ESSCIRC.1988.5468361","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468361","url":null,"abstract":"New driver and receiver circuits for WSI systems have been realized with the advantages of short delay, small area and low power dissipation. These concepts are compared to conventional driver circuits.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133357646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 4Gbits/sec GaAs BFL MESFET 4:1 Multiplexer 4gbps GaAs BFL MESFET 4:1多路复用器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/esscirc.1988.5468301
C. G. Eddison, M. Mudd, D. J. Warner, D. Parker
{"title":"A 4Gbits/sec GaAs BFL MESFET 4:1 Multiplexer","authors":"C. G. Eddison, M. Mudd, D. J. Warner, D. Parker","doi":"10.1109/esscirc.1988.5468301","DOIUrl":"https://doi.org/10.1109/esscirc.1988.5468301","url":null,"abstract":"We have designed and fabricated a GaAs buffered FET logic (BFL) 4:1 multiplexer using 0.7¿m gate length ion implanted MESFETs and Schottky diodes. The circuit, which exhibited excellent yields (62%), operated up to 4.1GBits/sec, with a DC power dissipation of 1.65Watts. The IC had 134 FETs, with a total gate periphery of 4.9mm, and 86 (6100¿m2) level shift diodes. In addition, 250pF of decoupling capacitance was provided on the 2.3mm × 2.0mm chip. The circuit formed one half of a multiplexer/demultiplexer demonstrator chip set, and was the first GaAs MESFET MSI circuit produced on our foundry process.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132735667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fully Integrated Analog Telephone 全集成模拟电话
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468316
E. Moons, E. Willocx, D. Rabaey
{"title":"Fully Integrated Analog Telephone","authors":"E. Moons, E. Willocx, D. Rabaey","doi":"10.1109/ESSCIRC.1988.5468316","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468316","url":null,"abstract":"The design of a CLSI for analog subset applications is presented. The MIP (Maximum Integrated Phone) combines extended signalling and speech functions in a single integrated circuit using a 2.4 micron CMOS technology. A loudspeaker amplifier included in the receive path permits on hook dialing and group listening. A synthesized high impedant current source extracts the power available on the line terminals. The noise requirements of -72 dBVp with 50 dB gain could be achieved by implementing a low noise preamplifier and with integration of a background noise reduction circuit in the transmit path. Packaged in a 40 pins DIL the MIP-device offers a cost effective solution for future low-, medium- and high-end subset applications.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128226559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
TITAN: An Universal Circuit Simulator with Event Control for Latency Exploitation 一个具有事件控制的通用电路模拟器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468362
U. Feldmann, R. Schultz
{"title":"TITAN: An Universal Circuit Simulator with Event Control for Latency Exploitation","authors":"U. Feldmann, R. Schultz","doi":"10.1109/ESSCIRC.1988.5468362","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468362","url":null,"abstract":"While for semicustom IC design a mixed mode simulator is ne¬ cessary which operates on the functional level in the time do¬ main, for full custom IC design a circuit simulator is required which operates very efficiently on the structural level in both the time domain and in the direct current and frequency domain. Our efforts concentrated upon a full custom simulator TITAN with the following basic features:","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126688741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
ALBA: A Bipolar Technology Structured Array For The Design Of Continuous Time Filters 用于连续时间滤波器设计的双极结构阵列
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468384
R. Gaidano, M. Mazzucco, M. Sartori
{"title":"ALBA: A Bipolar Technology Structured Array For The Design Of Continuous Time Filters","authors":"R. Gaidano, M. Mazzucco, M. Sartori","doi":"10.1109/ESSCIRC.1988.5468384","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468384","url":null,"abstract":"Fully integrated structured array is described here as implementing filters, the topology of which can be selected with only one process mask; the filter cutoff frequencies can track an external clock via a newly developed internal automatic frequency control.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121762948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10K-Gate 950MHz CML Demonstrator Circuit Made with a One-Micron, Trench Isolated Bipolar Silicon Technology 用一微米沟槽隔离双极硅技术制成的10k门950MHz CML演示电路
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468312
M. Depey, F. Dell'ova, J. Chateau, C. Mallardeau, A. Fryers, K. Woerner
{"title":"A 10K-Gate 950MHz CML Demonstrator Circuit Made with a One-Micron, Trench Isolated Bipolar Silicon Technology","authors":"M. Depey, F. Dell'ova, J. Chateau, C. Mallardeau, A. Fryers, K. Woerner","doi":"10.1109/ESSCIRC.1988.5468312","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468312","url":null,"abstract":"","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123515596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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