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ESSCIRC '88: Fourteenth European Solid-State Circuits Conference最新文献

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The Design of Single Chip Memory Management Unit/Data Cache 单片机存储管理单元/数据缓存的设计
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468474
A. K. Goksel, R. Krambeck, P. Thomas, M. Tsay
{"title":"The Design of Single Chip Memory Management Unit/Data Cache","authors":"A. K. Goksel, R. Krambeck, P. Thomas, M. Tsay","doi":"10.1109/ESSCIRC.1988.5468474","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468474","url":null,"abstract":"CAM-based translation mechanism and a large instruction data cache onto a single chip (Figure 1). Thib architecture combines high performance memory management with systemlevel caching to eliminate address translation overhead, and achieves the high hit rate and functionality of a physical-based cache. Fully automatic and feature-rich memory management support, and upward protocol and O S compatibility, are provided. The chip, fabricated using AT&T's lum Twin Tub CMOS, l contains approx. 400,000 transistors and is housed in a 133 pin pin-grid-array package. Power dissipation is about 1 watt at the operating frequency of 21 MHz. The silicon is currently fully operational at 24MHz and is available in preproduction quantities.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115622238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Monolithic Bipolar 16 × 16 (+16) Crosspoint Matrix with Optimized Power Consumption 具有优化功耗的单片双极16 × 16(+16)交叉点矩阵
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468317
J. Burkhart, J. Schomers
{"title":"A Monolithic Bipolar 16 × 16 (+16) Crosspoint Matrix with Optimized Power Consumption","authors":"J. Burkhart, J. Schomers","doi":"10.1109/ESSCIRC.1988.5468317","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468317","url":null,"abstract":"A bipolar 16×16(+16) crosspoint matrix for 140 Mbit/s communication systems is described. Low power consumption of less than 0.9 watt has been achieved by careful optimization of the signal network. The crosspoint matrix is capable of performing asynchronous, i.e. transparent switching of digital signals up to greater than 280 Mbit/s without an additional clock supply.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115654256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Very High Slew-Rate Dynamic CMOS Operational Amplifier 一种非常高回转速率动态CMOS运算放大器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468347
R. Klinke, B. Hosticka, H. Pfleiderer
{"title":"A Very High Slew-Rate Dynamic CMOS Operational Amplifier","authors":"R. Klinke, B. Hosticka, H. Pfleiderer","doi":"10.1109/ESSCIRC.1988.5468347","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468347","url":null,"abstract":"We present a dynamic CMOS operational amplifier with a special input circuit which injects an extra bias current to increase the slew-rate, depending on the input signal. The performance of this operational amplifier is compared to a conventional operational amplifier when used in a sample&hold circuit. The maximum operating clock frequency of the sample&hold circuit increases from 290 kHz up to 1 MHz with a hold-capacitor of 1 nF. The amplifier has been fabricated in a 5 ¿m CMOS process and dissipates a static power of 7.5 mW.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124865744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The Design and Production of Microwave Switch and Amplifier Modules Employing GaAs MMICs 基于砷化镓微芯片的微波开关与放大模块的设计与制作
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468372
R. Pengelly, A. Ezzeddine, B. Maoz
{"title":"The Design and Production of Microwave Switch and Amplifier Modules Employing GaAs MMICs","authors":"R. Pengelly, A. Ezzeddine, B. Maoz","doi":"10.1109/ESSCIRC.1988.5468372","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468372","url":null,"abstract":"GaAs MMIC technology and circuit design has matured over the last few years to a point where a number of products are now available commercially. Until recently these products have been single bare die or packaged single devices. Subsystem research and development centers have been building multi-chip modules for some time (ref. 1 & 2 for example), but there have been very few examples of such items being commercially available. This paper describes the design of a number of GaAs MMICs and the assembly of these parts into multi-chip modules built specifically as cost-effective products. Specific examples of driven multi-throw switches for EW, communications and test equipment applications are given together with details of amplifier modules containing voltage regulation and temperature compensation.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116864318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Present Status and Future Trends in Analog Design Automation 模拟设计自动化的现状与未来趋势
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468281
M. Degrauwe
{"title":"Present Status and Future Trends in Analog Design Automation","authors":"M. Degrauwe","doi":"10.1109/ESSCIRC.1988.5468281","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468281","url":null,"abstract":"","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128243073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel RISC Architecture for High-Speed Floating-Point Signal Processing 高速浮点信号处理的新型RISC架构
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468418
B. Yernaux, P. Jespers
{"title":"A Novel RISC Architecture for High-Speed Floating-Point Signal Processing","authors":"B. Yernaux, P. Jespers","doi":"10.1109/ESSCIRC.1988.5468418","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468418","url":null,"abstract":"This paper describes the Floating-point digital Signal Processor of UCL, the FSPU, which is a single chip 22-bit signal and speech processor. The FSPU has been conceived according to a RISC philosophy and is based on a novel Processing Unit that achieves very high computation throughputs, while taking the greatest advantage of the wide dynamic range and precision features of the floating-point arithmetic. The developed architecture is intended to go beyond the limits of the standard general-purpose DSP implementations and to make the floating-point arithmetic more attractive on speed level. A 3 ¿m CMOS prototype has been realized.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126820129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Family of Microprocessors with Non Volatile Memory for Smart Card Applications 智能卡应用的非易失性存储器微处理器系列
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468466
S. Fruhauf, L. Sourgen
{"title":"A Family of Microprocessors with Non Volatile Memory for Smart Card Applications","authors":"S. Fruhauf, L. Sourgen","doi":"10.1109/ESSCIRC.1988.5468466","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468466","url":null,"abstract":"This presentation report on a family of microprocessors with on board EPROM or EEPROM designed for smart card applications. Security devices, testing circuits and specific firmware have been included in this 1.5 micron CMOS module based design. An EPROM and an EEPROM chips are presented.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121289281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Mixed-Mode A/D Converter with Self-Testing Capability 一种具有自测能力的混合模A/D转换器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468460
C. Leme, J. Franca, F. Maloberti, M. Piedade
{"title":"A Mixed-Mode A/D Converter with Self-Testing Capability","authors":"C. Leme, J. Franca, F. Maloberti, M. Piedade","doi":"10.1109/ESSCIRC.1988.5468460","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468460","url":null,"abstract":"This paper describes a 15-bit resolution self-calibrated A/D conversion system which can also realise the complementary D/A conversion. This makes it possible to implement a closed loop D/A + A/D conversion which can be used for performing a self-testing of the converter.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126242828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Design Program for Comparators 比较器设计程序
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468352
C. Meixenberger, M. Degrauwe
{"title":"A Design Program for Comparators","authors":"C. Meixenberger, M. Degrauwe","doi":"10.1109/ESSCIRC.1988.5468352","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468352","url":null,"abstract":"A design program for CMOS voltage comparators based on a library of fixed schematics has been realized. The program starts from simplified analytic expressions and uses a fast built-in transient simulator in an iteration loop to converge towards a correct solution. The program takes into account device mismatches, clock feedthrough and noise which are important limitative parameters for the comparator performances. Experimental results agree with the designed values and are compared with SPICE simulation results.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121966740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 750 ks/s 8-Bit Low-Power Pipelined A/D Converter 一个750ks /s的8位低功耗流水线A/D转换器
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference Pub Date : 1988-09-01 DOI: 10.1109/ESSCIRC.1988.5468461
V. Valencic, P. Deval
{"title":"A 750 ks/s 8-Bit Low-Power Pipelined A/D Converter","authors":"V. Valencic, P. Deval","doi":"10.1109/ESSCIRC.1988.5468461","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468461","url":null,"abstract":"A switched-capacitor pipelined A/D convertor is described, in which the amplifier offset compensation is inherent to the circuit structure and the effect of clock-feedthrough is as low as 0.5 mV. Preliminary experimental results, obtained on circuits fabricated using a low-voltage CMOS technology, indicate 8- bit resolution for 750 kHz sampling frequency, with only 5 mW power consumption.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115886800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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