Sixth IEEE International High-Level Design Validation and Test Workshop最新文献_第2页

An enhanced cut-points algorithm in formal equivalence verification 形式等价验证中的一种改进切点算法

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972825

Z. Khasidashvili, J. Moondanos, Daher Kaiss, Z. Hanna

引用次数: 12

Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication 嵌入式多处理器SoC通信硬件/软件实现的快速时序协同仿真

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972811

S. Yoo, G. Nicolescu, L. Gauthier, A. Jerraya

引用次数: 4

Reducing bitvector satisfiability problems to scale down design sizes for RTL property checking 减少位向量可满足性问题，以缩小RTL属性检查的设计尺寸

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972818

P. Johannsen

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引用次数: 16

Symbolic simulation techniques-state-of-the-art and applications 符号仿真技术——最新技术及其应用

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972806

C. Blank, H. Eveking, Jens Levihn, G. Ritter

引用次数: 11

Observability enhanced coverage analysis of C programs for functional validation 可观察性增强了C程序的覆盖率分析，用于功能验证

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972823

F. Fallah, Indradeep Ghosh

{"title":"Observability enhanced coverage analysis of C programs for functional validation","authors":"F. Fallah, Indradeep Ghosh","doi":"10.1109/HLDVT.2001.972823","DOIUrl":"https://doi.org/10.1109/HLDVT.2001.972823","url":null,"abstract":"Software programs written in some programming languages like C, C++, Java, etc, are mostly verified by functional simulation. Since exhaustive functional simulation is impossible for even a small sized C program, it is important to quantitatively measure the extent of design verification during simulation by a set of test vectors. Various coverage metrics have been proposed for measuring the degree of design verification. Most of them compute the extent of design excitation (controllability) but are unable to say whether the excitation responses have propagated to observable points in the program (observability). In this paper we propose a metric for code coverage analysis of C programs that addresses not only controllability but tackles observability as well. Thus, this metric is able to tell what percentage of the simulation responses have been propagated to observable points in the program like primary outputs or printed variables. We improve upon a recently proposed observability enhanced software coverage metric by increasing the accuracy of the analysis as well as decreasing the simulation runtime overhead. We report some preliminary results on example C programs.","PeriodicalId":188469,"journal":{"name":"Sixth IEEE International High-Level Design Validation and Test Workshop","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128264606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model 基于端口顺序故障模型的SoC设计验证中数据路径元素最小模式集的生成

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972821

Chun-Yao Wang, S. Tung, Jing-Yang Jou

引用次数: 1

Relating buffer-oriented microarchitecture validation to high-level pipeline functionality 将面向缓冲区的微架构验证与高级管道功能联系起来

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972799

N. Utamaphethai, R. D. Blanton, John Paul Shen

引用次数: 4

Hardware-software covalidation: fault models and test generation 硬件软件协同验证:故障模型和测试生成

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972822

I. Harris

引用次数: 6

Improving test quality through resource reallocation 通过资源重新分配提高测试质量

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972809

Allon Adir, E. Marcus, M. Rimon, Amir Voskoboynik

引用次数: 6

Practical use of sequential ATPG for model checking: going the extra mile does pay off 实际使用顺序ATPG进行模型检查:付出额外的努力是值得的

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972805

M. Hsiao, J. Jain

引用次数: 14