Sixth IEEE International High-Level Design Validation and Test Workshop最新文献

Using live sequence charts for hardware protocol specification and compliance verification 使用实时序列图进行硬件协议规范和符合性验证

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972814

Annette Bunker, G. Gopalakrishnan

引用次数: 18

Proving sequential consistency by model checking 通过模型检查证明序列一致性

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972815

T. Braun, A. Condon, A. Hu, Kai S. Juse, Marius Laza, Michael Leslie, Rita Sharma

引用次数: 9

A language formalism for verification of PowerPC/sup TM/ custom memories using compositions of abstract specifications 一种使用抽象规范组合来验证PowerPC/sup TM/自定义内存的语言形式

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972820

J. Bhadra, Andrew K. Martin, J. Abraham, M. Abadir

引用次数: 5

Using cutwidth to improve symbolic simulation and Boolean satisfiability 利用切口宽度改进符号仿真和布尔可满足性

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972824

Dong Wang, E. Clarke, Yunshan Zhu, J. Kukula

引用次数: 23

Constraints specification at higher levels of abstraction 更高抽象层次的约束规范

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972819

F. Balarin, J. Burch, L. Lavagno, Yosinori Watanabe, R. Passerone, A. Sangiovanni-Vincentelli

引用次数: 38

Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description 根据组合逻辑块的功能描述估计测试集的相对单卡故障覆盖率

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972804

I. Pomeranz, S. Reddy

引用次数: 3

Integrating Perl, Tcl and C++ into simulation-based ASIC verification environments 将Perl, Tcl和c++集成到基于仿真的ASIC验证环境中

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972802

M. D. McKinney

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引用次数: 4

Experience with term level modeling and verification of the M*CORE/sup TM/ microprocessor core 具有M*CORE/sup TM/微处理器核心的术语级建模和验证经验

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972816

Shuvendu K. Lahiri, C. Pixley, Ken Albin

引用次数: 34

Automatic validation of pipeline specifications 自动验证管道规格

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972800

P. Mishra, N. Dutt, A. Nicolau

引用次数: 10

RTL functional verification using excitation and observation coverage RTL功能验证使用激励和观察覆盖

Sixth IEEE International High-Level Design Validation and Test Workshop Pub Date : 2001-12-07 DOI: 10.1109/HLDVT.2001.972808

Byeong Min, G. Choi

引用次数: 0