Integrating Perl, Tcl and C++ into simulation-based ASIC verification environments

Abstract

As ASIC designs become more complex, it follows that the complexity of the verification environments for such designs increases dramatically as well. However, while System-on-Chip methodologies and thought processes have been strongly accepted and utilized for the HDL design, there has not been a concurrent type of strong process taking place for verification environments. That is, the HDL of an ASIC design can be divided, even sub-divided, into understandable but reasonably sized components whose behavior can be comprehended in a reasonable amount of time However, any verification environment that is created or generated for these design sub-blocks remains highly complex, whether written in HDL or any of the various verification or scripting languages now available. This paper will address issues faced and lessons learned by an ASIC design team whose product is a highly complex SOC-based design. The team's desire was to integrate C++, Tcl and Perl together in a coherent, highly intelligent and usable verification environment for the ASIC. This effort was highly successful (although there have been some less encouraging moments along the way) and the resulting simulation environment is being used now with acceptable results.